144 lines
3.2 KiB
Verilog
144 lines
3.2 KiB
Verilog
module WarpSE(
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input [23:1] A_FSB,
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input nAS_FSB,
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input nLDS_FSB,
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input nUDS_FSB,
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input nWE_FSB,
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output nDTACK_FSB,
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output nVPA_FSB,
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output nBERR_FSB,
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input FCLK,
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input C16M,
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input C8M,
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input E,
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input nDTACK_IOB,
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input nVPA_IOB,
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output nVMA_IOB,
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output nAS_IOB,
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output nUDS_IOB,
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output nLDS_IOB,
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output nBR_IOB,
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input nBG_IOB,
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input nBERR_IOB,
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inout nRES,
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input nIPL2,
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output nROMCS,
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output nRAMLWE,
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output nRAMUWE,
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output nROMWE,
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output nRAS,
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output nCAS,
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output [11:0] RA,
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output nOE,
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output nADoutLE0,
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output nADoutLE1,
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output nAoutOE,
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output nDoutOE,
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output nDinOE,
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output nDinLE,
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input [3:1] SW,
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output C20MEN,
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output C25MEN);
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/* FSB clock oscillator enables */
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// Enable both oscillators... only mount one
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assign C20MEN = 1;
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assign C25MEN = 1;
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/* Reset input and open-drain output */
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wire nRESin = nRES;
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wire nRESout;
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assign nRES = !nRESout ? 1'b0 : 1'bZ;
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/* AS cycle detection */
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wire BACT;
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/* Refresh request/ack signals */
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wire RefReq, RefUrg;
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/* FSB chip select signals */
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wire IOCS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR;
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CS cs(
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/* MC68HC000 interface */
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A_FSB[23:08], FCLK, nRESin, nWE_FSB,
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/* AS cycle detection */
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BACT,
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/* Device select outputs */
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IOCS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR);
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wire RAM_Ready;
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RAM ram(
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/* MC68HC000 interface */
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FCLK, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
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/* AS cycle detection */
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BACT,
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/* Select and ready signals */
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RAMCS, ROMCS, RAM_Ready,
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/* Refresh Counter Interface */
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RefReq, RefUrg,
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/* DRAM and NOR flash interface */
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RA[11:0], nRAS, nCAS,
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nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
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wire IOBS_Ready;
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wire IOREQ, IOACT, IOBERR;
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wire ALE0S, ALE0M, ALE1;
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assign nADoutLE0 = ~(ALE0S || ALE0M);
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assign nADoutLE1 = ~ALE1;
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wire IORW0, IOL0, IOU0;
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IOBS iobs(
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/* MC68HC000 interface */
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FCLK, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
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/* AS cycle detection, FSB BERR */
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BACT,
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/* Select and ready signals */
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IOCS, IOPWCS, IOBS_Ready, nBERR_FSB,
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/* Read data OE control */
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nDinOE,
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/* IOB Master Controller Interface */
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IOREQ, IOACT, IOBERR,
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/* FIFO primary level control */
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ALE0S, IORW0, IOL0, IOU0,
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/* FIFO secondary level control */
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ALE1);
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wire AoutOE;
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assign nAoutOE = !AoutOE;
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wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
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assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
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assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
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assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
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assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
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IOBM iobm(
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/* PDS interface */
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C16M, C8M, E,
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nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
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nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
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/* PDS address and data latch control */
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AoutOE, nDoutOE, ALE0M, nDinLE,
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/* IO bus slave port interface */
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IOACT, IOBERR,
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IOREQ, IOL0, IOU0, !IORW0);
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CNT cnt(
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/* FSB clock and E clock inputs */
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FCLK, E,
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/* Refresh request */
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RefReq, RefUrg,
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/* Reset, button */
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nRESout, nIPL2,
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/* Mac PDS bus master control outputs */
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AoutOE, nBR_IOB);
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FSB fsb(
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/* MC68HC000 interface */
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FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
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/* FSB cycle detection */
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BACT,
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/* Ready inputs */
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RAM_Ready, IOBS_Ready, 1,
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/* Interrupt acknowledge select */
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IACS);
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endmodule
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