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33 lines
993 B
Verilog
33 lines
993 B
Verilog
module FSB(
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/* MC68HC000 interface */
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input FCLK, input nAS, output reg nDTACK, output reg nVPA,
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/* AS cycle detection */
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output reg ASrf, output BACT, output reg BACTr,
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/* Ready inputs */
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input ROMCS, input ROMReady,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input QoSEN,
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/* Interrupt acknowledge select */
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input IACKCS);
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/* AS cycle detection */
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always @(negedge FCLK) begin ASrf <= !nAS; end
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assign BACT = !nAS || ASrf; // BACT - bus active
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always @(posedge FCLK) BACTr <= BACT;
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/* DTACK/VPA control */
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wire Ready = (RAMCS && RAMReady && !QoSEN && !IOPWCS) ||
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(RAMCS && RAMReady && !QoSEN && IOPWCS && IOPWReady) ||
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(ROMCS && ROMReady && !QoSEN) || (IONPReady);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nDTACK <= 1;
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else if (!IACKCS && Ready) nDTACK <= 0;
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end
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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else if (IACKCS && IOPWReady) nVPA <= 0;
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end
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endmodule
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