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https://github.com/garrettsworkshop/Warp-SE.git
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132 lines
3.5 KiB
Verilog
132 lines
3.5 KiB
Verilog
module CNT(
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/* FSB clock and E clock inputs */
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input CLK, input C8M, input E,
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/* Refresh request */
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output reg RefReq, output reg RefUrg,
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/* Reset, button */
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output reg nRESout, input nRESin, input nIPL2,
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output reg nBR_IOB,
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/* QoS select inputs */
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input nAS,
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input ASrf,
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input BACT,
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input QoSCS,
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input SndQoSCS,
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/* QoS outputs */
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output reg QoSEN,
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output SndQoSReady,
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output reg MCKE);
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/* E clock synchronization */
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reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E };
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wire EFall = Er[1] && !Er[0];
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/* C8M clock synchronization */
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reg [3:0] C8Mr; always @(posedge CLK) C8Mr[3:0] <= { C8Mr[2:0], C8M };
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wire C8MFall = C8Mr[1] && !C8Mr[0]; // C8M falling edge detect
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/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
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* Refresh timer sequence
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* | Timer | RefReq | RefUrg |
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* |---------|--------|-----------|
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* | 0 0000 | 0 | 0 |
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* | 1 0001 | 1 | 0 |
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* | 2 0010 | 1 | 0 |
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* | 3 0011 | 1 | 0 |
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* | 4 0100 | 1 | 0 |
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* | 5 0101 | 1 | 0 |
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* | 6 0110 | 1 | 0 |
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* | 7 0111 | 1 | 0 |
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* | 8 1000 | 1 | 0 |
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* | 9 1001 | 1 | 1 |
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* | 10 1010 | 1 | 1 |
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* back to timer==0
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*/
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reg [3:0] Timer = 0;
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wire TimerTC = Timer==10;
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reg TimerTick;
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always @(posedge CLK) begin
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if (EFall) begin
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if (TimerTC) Timer <= 0;
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else Timer <= Timer+1;
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RefReq <= Timer!=10;
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RefUrg <= Timer==8 || Timer==9;
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end
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end
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always @(posedge CLK) TimerTick <= EFall && TimerTC;
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/* QoS select latches */
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reg QoSCSr, SndQoSCSr;
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always @(posedge CLK) QoSCSr <= (BACT && QoSCS) || !nRESin;
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always @(posedge CLK) SndQoSCSr <= BACT && SndQoSCS;
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/* QoS timer
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* In the absence of a QoS trigger, QS==0.
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* When Qos triggered, QS is set to 1 and counts 1, 2, 3, 0.
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* While QS!=0, QoS is enabled.
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* QoS enable period is 196.588 us - 210.630 us */
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reg [3:0] QS;
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always @(posedge CLK) begin
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if (SndQoSCSr || QoSCSr) QS <= 15;
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else if (QS==0) QS <= 0;
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else if (TimerTick) QS <= QS-1;
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end
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/* QoS enable control */
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always @(posedge CLK) if (!BACT) QoSEN <= QS!=0;
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assign SndQoSReady = 1;
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/* MC68k clock gating during QoS */
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always @(negedge CLK, negedge nAS) begin
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if (!nAS) MCKE <= 1;
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else MCKE <= ASrf || !QoSEN || C8MFall;
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end
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/* Long timer counts from 0 to 4095.
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* 4096 states == 57.516 ms */
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reg [11:0] LTimer;
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wire LTimerTC = LTimer[11:0]==12'hFFF;
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reg LTimerTick;
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always @(posedge CLK) if (TimerTick) LTimer <= LTimer+1;
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always @(posedge CLK) LTimerTick <= TimerTick && LTimerTC;
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/* C8M duty cycle check and power-on reset */
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reg nPOR = 0;
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always @(posedge CLK) begin
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if (C8Mr[3:0]==4'b0000 || C8Mr[3:0]==4'b1111) nPOR <= 0;
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else if (C8Mr[1:0]==2'b01) nPOR <= 1;
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end
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/* Startup sequence state control */
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reg [1:0] IS = 0;
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always @(posedge CLK) begin
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if (!nPOR) IS <= 0;
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else case (IS[1:0])
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0: if (LTimerTick) IS <= 1;
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1: if (LTimerTick) IS <= 2;
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2: if (LTimerTick && nIPL2) IS[0] <= 1;
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3: IS <= 3;
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endcase
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end
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/* Startup sequence */
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always @(posedge CLK) begin
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case (IS[1:0])
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0, 1: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nBR_IOB <= 0; // Default to request bus
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end 2: begin
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AoutOE <= 0;
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nRESout <= 0;
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if (!nIPL2) nBR_IOB <= 1; // Disable bus request if NMI pressed
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end 3: begin
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AoutOE <= !nBR_IOB;
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if (LTimerTick) nRESout <= 1; // Release reset after a while
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end
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endcase
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end
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endmodule
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