108 lines
2.7 KiB
Verilog
108 lines
2.7 KiB
Verilog
module CNT(
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/* C16M clock */
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input C16M,
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/* FSB clock and bus active signal */
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input FCLK, input BACT,
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/* Refresh request */
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output reg RefReq, output RefUrgent,
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/* BERR and QoS speed limit output */
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output reg BERRTimeout, output reg QoSGate,
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/* Reset, switch, button */
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input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
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/* Configuration outputs */
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output reg nBR_IOB, output reg FastROMEN, output reg C20MEN, output reg C25MEN);
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/* Timer counts from 0 to 11100000 (224) -- 225 states == 14.36 uS */
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reg [7:0] Timer = 0;
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wire TimerTC = Timer[7:5]==3'b111;
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always @(posedge C16M) Timer <= TimerTC ? 0 : Timer+1;
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/* Refresh timer outputs
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* ___ ______________________________________
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* RefReq |___________| |__________
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* ___ ^ Timer==0 ^ Timer==17 _____________^ Timer==0
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* RefUrg |____________________________________| |__________
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* ^ Timer==0 ^ Timer==128 ^ Timer==0
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*/
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assign RefUrgent = Timer[7];
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always @(posedge C16M) begin
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if (Timer[4]) RefREQ <= 1;
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else if (TimerTC) RefREQ <= 0;
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end
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/* NBACT - "Narrow BACT" in FCLK clock domain */
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reg [1:0] BACTCnt = 0;
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reg NBACT;
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always @(posedge FCLK) begin
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if (!BACT) begin
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BACTCnt <= 0;
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NBACT <= 0;
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end else begin
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BACTCnt <= BACTCnt+1;
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if (BACTCnt==2'b11 && BACT) NBACT <= 1;
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end
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end
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/* NBACTr - NBACT synchronized to C16M clock domain */
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reg NBACTr;
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always @(posedge C16M) NBACTr <= NBACT;
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/* BERR generation in C16M clock domain */
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reg BERRArm = 0;
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reg BERRTimeout = 0;
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always @(posedge C16M) begin
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if (NBACTr && TimerTC) begin
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BERRArm <= 1;
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if (BERRArm) BERRTimeout <= 1;
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end else if (!NBACTr) begin
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BERRArm <= 0;
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BERRTimeout <= 0;
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end
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end
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/* Sound QoS counter */
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reg [13:0] SC; // Sound counter
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always @(posedge C16M) begin
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if (TimerTC) SC <= SC+1; // SC increment
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end
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/* IPL2 registration */
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reg nIPL2r, nRESr;
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always @(negedge C16M) begin
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nIPL2r <= nIPL2;
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nRESr <= nRES;
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end
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/* Startup sequence control */
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reg [1:0] PORS = 0;
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always @(posedge C16M) begin
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case (PORS)
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0: begin
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nRESout <= !nRESr;
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if (nRESr) PORS <= 1;
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end 1: begin
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nRESout <= 0;
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if (TimerTC && SC[13:0]==14'h3FFF && nIPL2r) PORS <= 2;
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end 2: begin
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nRESout <= 0;
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if (TimerTC && SC[13:0]==14'h3FFF) PORS <= 3;
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end 3: begin
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nRESout <= 1;
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end
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endcase
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end
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/* Accelerator enable/disable control */
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always @(posedge CLK) begin
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if (PORS==0) begin
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if (nRESr) nBR_IOB <= nIPL2r;
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else nBR_IOB <= 1;
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end
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end
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// Enable both oscillators... only mount one
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assign C20MEN = 1;
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assign C25MEN = 1;
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endmodule
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