125 lines
3.3 KiB
Verilog
125 lines
3.3 KiB
Verilog
module CNT(
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/* C8M clock input */
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input C8M,
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/* FSB clock and bus active signal */
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input FCLK, input LBACT,
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/* Refresh request */
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output reg RefReq, output RefUrgent,
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/* BERR output */
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output reg BERRTimeout,
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/* Reset, switch, button */
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input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output nAoutOE, output nBR_IOB,
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/* Configuration outputs */
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output reg WarpEnable, output reg FastROMEN, output C20MEN, output C25MEN);
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/* Timer counts from 0 to 1100000 (96) -- 97 states == 12.382 us */
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reg [6:0] Timer = 0;
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wire TimerTC = Timer[6:5]==2'b11;
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always @(posedge C8M) Timer <= TimerTC ? 0 : Timer+1;
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/* Refresh timer sequence
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* | Timer | RefReq | RefUrgent |
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* |----------------------------|
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* | 0 | 0 | 0 |
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* | 1 | 0 | 0 |
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* | 2 | 0 | 0 |
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* | 3 | 0 | 0 |
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* | 4 | 0 | 0 |
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* | 5 | 0 | 0 |
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* | 6 | 0 | 0 |
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* | 7 | 0 | 0 |
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* | 8 | 0 | 0 |
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* | 9 | 1 | 0 |
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* | 10 | 1 | 0 |
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* | 11 | 1 | 0 |
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* | ... | 1 | 0 |
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* | 62 | 1 | 0 |
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* | 63 | 1 | 0 |
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* | 64 | 1 | 1 |
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* | 65 | 1 | 1 |
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* | 66 | 1 | 1 |
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* | ... | 1 | 1 |
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* | 93 | 1 | 1 |
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* | 94 | 1 | 1 |
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* | 95 | 1 | 1 |
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* | 96 | 1 | 1 |
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* back to timer==0
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*/
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assign RefUrgent = Timer[6];
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always @(posedge C8M) begin
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if (Timer[3]) RefReq <= 1;
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else if (TimerTC) RefReq <= 0;
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end
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/* LBACTr - LBACT synchronized to C16M clock domain */
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reg LBACTr;
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always @(posedge C8M) LBACTr <= LBACT;
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/* BERR generation in C8M clock domain */
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reg BERRArm = 0;
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always @(posedge C8M) begin
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if (LBACTr && TimerTC) begin
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BERRArm <= 1;
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if (BERRArm) BERRTimeout <= 1;
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end else if (!LBACTr) begin
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BERRArm <= 0;
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BERRTimeout <= 0;
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end
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end
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/* Long timer counts from 0 to 16384 -- 16385 states == 202.888 ms */
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reg [14:0] LTimer; // Long timer
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wire LTimerTC = LTimer[14];
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always @(posedge C8M) begin
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if (LTimerTC) LTimer <= 0;
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else LTimer <= LTimer+1;
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end
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/* IPL2 synchronizer */
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reg IPL2r;
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always @(posedge C8M) IPL2r <= !nIPL2;
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/* Startup sequence control */
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reg [1:0] PORS = 0;
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reg Disable = 0;
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reg BR_IOB = 0; assign nBR_IOB = !BR_IOB;
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assign nAoutOE = !AoutOE;
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always @(posedge C8M) begin
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case (PORS)
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0: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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Disable <= 0;
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if (LTimerTC) PORS <= 1;
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end 1: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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Disable <= Disable | IPL2r;
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if (!IPL2r && LTimerTC) begin
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BR_IOB <= !Disable;
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PORS <= 2;
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end
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end 2: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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if (LTimerTC) PORS <= 3;
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end 3: begin
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AoutOE <= BR_IOB;
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// Wait until LTimerTC to release reset
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if (LTimerTC) nRESout <= 1;
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else nRESout = 0;
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PORS <= 3;
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end
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endcase
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end
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// Enable both oscillators... only mount one
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assign C20MEN = 1;
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assign C25MEN = 1;
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// Enable fast ROM
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assign FastROMEN = 1;
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endmodule
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