mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-25 13:33:58 +00:00
920 lines
55 KiB
Plaintext
920 lines
55 KiB
Plaintext
Performance Summary Report
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--------------------------
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Design: WarpSE
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Device: XC95144XL-10-TQ100
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Speed File: Version 3.0
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Program: Timing Report Generator: version P.20131013
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Date: Mon Mar 28 09:28:06 2022
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Timing Constraint Summary:
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TS_CLK_IOB=PERIOD:CLK_IOB:142.857nS:HIGH:71.428nS N/A
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TS_CLK_FSB=PERIOD:CLK_FSB:40.000nS:HIGH:20.000nS Met
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TS_CLK2X_IOB=PERIOD:CLK2X_IOB:66.666nS:HIGH:33.333nS Met
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Performance Summary:
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Pad to Pad (tPD) : 11.0ns (1 macrocell levels)
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Pad 'A_FSB<11>' to Pad 'RA<1>'
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Clock net 'CLK_IOB' path delays:
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Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)
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Data signal 'E_IOB' to DFF D input Pin at 'iobm/Er.D'
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Clock pad 'CLK_IOB' (GCK)
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Minimum Clock Period: 9.0ns
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Maximum Internal Clock Speed: 111.1Mhz
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(Limited by Clock Pulse Width)
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Clock net 'CLK_FSB' path delays:
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Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
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Clock Pad 'CLK_FSB' to Output Pad 'RA<1>' (GCK)
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Clock to Setup (tCYC) : 20.1ns (2 macrocell levels)
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Clock to Q, net 'cs/nOverlay1.Q' to DFF Setup(D) at 'fsb/VPA.D' (GCK)
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Target FF drives output net 'fsb/VPA'
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Setup to Clock at the Pad (tSU) : 16.6ns (1 macrocell levels)
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Data signal 'A_FSB<23>' to DFF D input Pin at 'fsb/VPA.D'
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Clock pad 'CLK_FSB' (GCK)
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Minimum Clock Period: 20.1ns
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Maximum Internal Clock Speed: 49.7Mhz
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(Limited by Cycle Time)
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Clock net 'CLK2X_IOB' path delays:
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Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
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Clock Pad 'CLK2X_IOB' to Output Pad 'nVMA_IOB' (GCK)
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Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
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Clock to Q, net 'iobm/IOS_FSM_FFd3.Q' to DFF Setup(D) at 'IOACT.D' (GCK)
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Target FF drives output net 'IOACT'
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Setup to Clock at the Pad (tSU) : 7.5ns (0 macrocell levels)
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Data signal 'CLK_IOB' to DFF D input Pin at 'IOACT.D'
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Clock pad 'CLK2X_IOB' (GCK)
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Minimum Clock Period: 11.0ns
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Maximum Internal Clock Speed: 90.9Mhz
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(Limited by Cycle Time)
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--------------------------------------------------------------------------------
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Pad to Pad (tPD) (nsec)
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\ From A A A A A A A A A A A
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\ _ _ _ _ _ _ _ _ _ _ _
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\ F F F F F F F F F F F
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\ S S S S S S S S S S S
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\ B B B B B B B B B B B
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\ < < < < < < < < < < <
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\ 1 1 1 1 1 1 1 1 1 1 1
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\ 0 1 2 3 4 5 6 7 8 9 >
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\ > > > > > > > > > >
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To \------------------------------------------------------------------
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CLK20EN
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CLK25EN
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RA<0> 10.0 10.0
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RA<10>
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RA<11> 10.0
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RA<1> 11.0
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RA<2> 11.0
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RA<3> 10.0
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RA<4> 11.0
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RA<5> 11.0
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RA<6> 10.0
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RA<7> 10.0
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RA<8> 10.0
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RA<9> 10.0
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nBERR_FSB
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nDinOE
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nOE
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nRAMLWE
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nRAMUWE
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nRAS
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nROMCS
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nROMWE
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nVPA_FSB
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--------------------------------------------------------------------------------
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Pad to Pad (tPD) (nsec)
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\ From A A A A A A A A A A A
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\ _ _ _ _ _ _ _ _ _ _ _
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\ F F F F F F F F F F F
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\ S S S S S S S S S S S
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\ B B B B B B B B B B B
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\ < < < < < < < < < < <
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\ 2 2 2 2 2 3 4 5 6 7 8
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\ 0 1 2 3 > > > > > > >
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\ > > > >
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To \------------------------------------------------------------------
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CLK20EN
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CLK25EN
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RA<0>
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RA<10> 10.0
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RA<11>
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RA<1> 11.0
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RA<2> 11.0
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RA<3> 10.0
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RA<4> 11.0
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RA<5> 11.0
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RA<6> 10.0
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RA<7> 10.0
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RA<8> 11.0 11.0 11.0
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RA<9> 10.0
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nBERR_FSB 11.0 11.0 11.0 11.0
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nDinOE 10.0 10.0 10.0 10.0
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nOE
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nRAMLWE
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nRAMUWE
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nRAS 11.0 11.0 11.0
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nROMCS 11.0 11.0 11.0 11.0
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nROMWE
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nVPA_FSB
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--------------------------------------------------------------------------------
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Pad to Pad (tPD) (nsec)
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\ From A S S n n n n
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\ _ W W A L U W
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\ F < < S D D E
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\ S 0 1 _ S S _
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\ B > > F _ _ F
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\ < S F F S
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\ 9 B S S B
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\ > B B
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\
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To \------------------------------------------
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CLK20EN 10.0
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CLK25EN 10.0
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RA<0>
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RA<10>
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RA<11>
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RA<1>
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RA<2>
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RA<3>
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RA<4>
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RA<5>
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RA<6>
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RA<7>
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RA<8> 11.0
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RA<9>
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nBERR_FSB 10.0
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nDinOE 10.0 10.0 10.0
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nOE 10.0 10.0
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nRAMLWE 10.0 10.0 10.0
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nRAMUWE 11.0 11.0 11.0
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nRAS 11.0
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nROMCS 11.0
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nROMWE 10.0 10.0
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nVPA_FSB 10.0
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--------------------------------------------------------------------------------
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Clock Pad to Output Pad (tCO) (nsec)
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\ From C C
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\ L L
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\ K K
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\ 2 _
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\ X F
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\ _ S
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\ I B
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\ O
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\ B
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\
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To \------------
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RA<0> 13.5
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RA<1> 14.5
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RA<2> 14.5
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RA<3> 13.5
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RA<4> 14.5
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RA<5> 14.5
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RA<6> 13.5
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RA<7> 13.5
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RA<8> 14.5
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RA<9> 13.5
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nADoutLE0 13.5 13.5
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nADoutLE1 5.8
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nAS_IOB 14.5
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nAoutOE 5.8
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nBERR_FSB 14.5
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nBR_IOB 5.8
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nCAS 5.8
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nDTACK_FSB 5.8
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nDinLE 5.8
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nDoutOE 5.8
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nLDS_IOB 14.5
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nRAMLWE 13.5
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nRAMUWE 14.5
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nRAS 14.5
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nROMCS 14.5
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nUDS_IOB 14.5
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nVMA_IOB 14.5
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nVPA_FSB 13.5
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--------------------------------------------------------------------------------
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Setup to Clock at Pad (tSU or tSUF) (nsec)
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\ From C C C
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\ L L L
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\ K K K
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\ 2 _ _
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\ X F I
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\ _ S O
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\ I B B
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\ O
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\ B
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\
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To \------------------
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A_FSB<10> 7.9
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A_FSB<11> 7.9
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A_FSB<12> 7.9
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A_FSB<13> 7.9
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A_FSB<14> 7.9
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A_FSB<15> 7.9
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A_FSB<16> 7.9
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A_FSB<17> 7.9
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A_FSB<18> 7.9
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A_FSB<19> 7.9
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A_FSB<20> 15.6
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A_FSB<21> 16.6
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A_FSB<22> 16.6
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A_FSB<23> 16.6
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A_FSB<8> 7.9
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A_FSB<9> 7.9
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CLK_IOB 7.5
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E_IOB 6.5
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SW<1> 7.9
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nAS_FSB 15.6
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nBERR_IOB 7.5
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nBG_IOB 6.5
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nDTACK_IOB 6.5
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nIPL2 6.5
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nLDS_FSB 6.5
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nRES 6.5 6.5
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nUDS_FSB 6.5
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nVPA_IOB 6.5
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nWE_FSB 7.9
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: CLK_FSB)
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\ From B I I I R R R R R T
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\ E O P P E E E E e i
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\ R R L L S S S S f m
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\ R W 2 2 D r r r A e
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\ _ 0 r r o 0 1 2 c o
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\ I . 0 1 n . . . k u
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\ O Q . . e Q Q Q . t
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\ B Q Q . Q A
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\ S Q .
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\ . Q
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\ Q
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\
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\
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\
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\
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\
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\
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\
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To \------------------------------------------------------------
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ALE0S.D
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BERR_IOBS.D 10.0
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IOL0.CE
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IOL0.D
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IOREQ.D
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IORW0.D 11.4
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IOU0.CE
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IOU0.D
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IPL2r1.D 10.0
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RESDone.CE 10.0 10.0 10.0
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RESr1.D 10.0
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RESr2.D 10.0
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RefAck.D
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TimeoutA.D 10.0
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TimeoutB.D
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cnt/RefCnt<1>.D
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cnt/RefCnt<2>.D
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cnt/RefCnt<3>.D
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cnt/RefCnt<4>.D
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cnt/RefCnt<5>.D
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cnt/RefCnt<6>.D
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cnt/RefCnt<7>.D
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cnt/RefDone.D 10.0
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cnt/TimeoutBPre.D
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cs/nOverlay0.D
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cs/nOverlay1.CE
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cs/nOverlay1.D
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fsb/BERR0r.D
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fsb/BERR1r.D 10.0
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fsb/Ready0r.D
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fsb/Ready1r.D
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fsb/Ready2r.D 11.0
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fsb/VPA.D 11.4 11.4
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iobs/Clear1.D
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iobs/IOL1.CE
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iobs/IORW1.D
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iobs/IOReady.D
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iobs/IOU1.CE
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iobs/Load1.D
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iobs/Once.D
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iobs/PS_FSM_FFd1.D
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iobs/PS_FSM_FFd2.D
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nADoutLE1.D
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nBR_IOB.CE 10.0 10.0 10.0 10.0 10.0 10.0
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nCAS.D
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nDTACK_FSB.D 11.4 11.4
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ram/BACTr.D
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ram/Once.D
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ram/RAMDIS1.D
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ram/RAMDIS2.D
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ram/RAMReady.D
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ram/RASEL.D
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ram/RS_FSM_FFd1.D
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ram/RS_FSM_FFd2.D
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ram/RS_FSM_FFd3.D
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: CLK_FSB)
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\ From T c c c c c c c c c
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\ i n n n n n n n n n
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\ m t t t t t t t t t
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\ e / / / / / / / / /
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\ o R R R R R R R R R
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\ u e e e e e e e e e
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\ t f f f f f f f f f
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\ B C C C C C C C C D
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\ . n n n n n n n n o
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\ Q t t t t t t t t n
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\ < < < < < < < < e
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\ 0 1 2 3 4 5 6 7 .
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\ > > > > > > > > Q
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\ . . . . . . . .
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\ Q Q Q Q Q Q Q Q
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\
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\
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\
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To \------------------------------------------------------------
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ALE0S.D
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BERR_IOBS.D
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IOL0.CE
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IOL0.D
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IOREQ.D
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IORW0.D
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IOU0.CE
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IOU0.D
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IPL2r1.D
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RESDone.CE
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RESr1.D
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RESr2.D
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RefAck.D
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TimeoutA.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
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TimeoutB.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
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cnt/RefCnt<1>.D 10.0
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cnt/RefCnt<2>.D 10.0 10.0
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cnt/RefCnt<3>.D 10.0 10.0 10.0
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cnt/RefCnt<4>.D 10.0 10.0 10.0 10.0
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cnt/RefCnt<5>.D 10.0 10.0 10.0 10.0 10.0
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cnt/RefCnt<6>.D 10.0 10.0 10.0 10.0 10.0 10.0
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cnt/RefCnt<7>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
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cnt/RefDone.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
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cnt/TimeoutBPre.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
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cs/nOverlay0.D
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cs/nOverlay1.CE
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cs/nOverlay1.D
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fsb/BERR0r.D 10.0
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fsb/BERR1r.D
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fsb/Ready0r.D
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fsb/Ready1r.D
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fsb/Ready2r.D
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fsb/VPA.D 19.1
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iobs/Clear1.D
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iobs/IOL1.CE
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iobs/IORW1.D
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iobs/IOReady.D
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iobs/IOU1.CE
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iobs/Load1.D
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iobs/Once.D
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iobs/PS_FSM_FFd1.D
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iobs/PS_FSM_FFd2.D
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nADoutLE1.D
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nBR_IOB.CE
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nCAS.D
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nDTACK_FSB.D 19.1
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ram/BACTr.D
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ram/Once.D
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ram/RAMDIS1.D 11.4 11.4 11.4 11.4
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ram/RAMDIS2.D 11.0 11.0 11.0 11.0
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ram/RAMReady.D 11.4 11.4 11.4 11.4
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ram/RASEL.D 11.4 11.4 11.4 11.4
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ram/RS_FSM_FFd1.D
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ram/RS_FSM_FFd2.D 11.4 11.4 11.4 11.4
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ram/RS_FSM_FFd3.D 11.0 11.0 11.0 11.0
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: CLK_FSB)
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\ From c c c f f f f f f f
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\ n s s s s s s s s s
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\ t / / b b b b b b b
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\ / n n / / / / / / /
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\ T O O A B B R R R V
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\ i v v S E E e e e P
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\ m e e r R R a a a A
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\ e r r f R R d d d .
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\ o l l . 0 1 y y y Q
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\ u a a Q r r 0 1 2
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\ t y y . . r r r
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\ B 0 1 Q Q . . .
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\ P . . Q Q Q
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\ r Q Q
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\ e
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\ .
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\ Q
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\
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To \------------------------------------------------------------
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ALE0S.D
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BERR_IOBS.D 10.0
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IOL0.CE
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IOL0.D
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IOREQ.D 11.0 10.0
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IORW0.D 10.0 11.0
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IOU0.CE
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IOU0.D
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IPL2r1.D
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RESDone.CE
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RESr1.D
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RESr2.D
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RefAck.D
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TimeoutA.D 10.0
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TimeoutB.D 10.0 10.0
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cnt/RefCnt<1>.D
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cnt/RefCnt<2>.D
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cnt/RefCnt<3>.D
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cnt/RefCnt<4>.D
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cnt/RefCnt<5>.D
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cnt/RefCnt<6>.D
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cnt/RefCnt<7>.D
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cnt/RefDone.D
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cnt/TimeoutBPre.D 10.0 10.0
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cs/nOverlay0.D 10.0 10.0
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cs/nOverlay1.CE 10.0
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cs/nOverlay1.D 10.0
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fsb/BERR0r.D 10.0 10.0
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fsb/BERR1r.D 10.0 10.0
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fsb/Ready0r.D 10.0 10.0 10.0
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fsb/Ready1r.D 11.0 10.0 11.0
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fsb/Ready2r.D 11.0 11.0 11.0
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fsb/VPA.D 20.1 19.1 11.4 11.4 20.1 11.4 11.4 11.4
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iobs/Clear1.D
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iobs/IOL1.CE
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iobs/IORW1.D 11.4 11.0
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iobs/IOReady.D 10.0
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iobs/IOU1.CE
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iobs/Load1.D 11.0 10.0
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iobs/Once.D 11.4 10.0
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iobs/PS_FSM_FFd1.D
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iobs/PS_FSM_FFd2.D 11.0 10.0
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nADoutLE1.D
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nBR_IOB.CE
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nCAS.D
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nDTACK_FSB.D 20.1 11.0 11.4 11.4 20.1 11.4 11.4
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ram/BACTr.D 10.0
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ram/Once.D 10.0 10.0
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ram/RAMDIS1.D 11.4 11.0
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ram/RAMDIS2.D 11.0 11.0
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ram/RAMReady.D 11.0 11.0
|
|
ram/RASEL.D 11.4 11.4
|
|
ram/RS_FSM_FFd1.D 10.0 10.0
|
|
ram/RS_FSM_FFd2.D 11.4 11.4
|
|
ram/RS_FSM_FFd3.D 11.0 11.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: CLK_FSB)
|
|
|
|
\ From i i i i i i i i i i
|
|
\ o o o o o o o o o o
|
|
\ b b b b b b b b b b
|
|
\ s s s s s s s s s s
|
|
\ / / / / / / / / / /
|
|
\ C I I I I I L O P P
|
|
\ l O O O O O o n S S
|
|
\ e A L R R U a c _ _
|
|
\ a C 1 W e 1 d e F F
|
|
\ r T . 1 a . 1 . S S
|
|
\ 1 r Q . d Q . Q M M
|
|
\ . . Q y Q _ _
|
|
\ Q Q . F F
|
|
\ Q F F
|
|
\ d d
|
|
\ 1 2
|
|
\ . .
|
|
\ Q Q
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0S.D 10.0 10.0
|
|
BERR_IOBS.D 10.0 10.0 10.0
|
|
IOL0.CE 10.0 10.0
|
|
IOL0.D 10.0
|
|
IOREQ.D 10.0 10.0 10.0 11.0
|
|
IORW0.D 11.0 11.4 11.4 11.4
|
|
IOU0.CE 10.0 10.0
|
|
IOU0.D 10.0
|
|
IPL2r1.D
|
|
RESDone.CE
|
|
RESr1.D
|
|
RESr2.D
|
|
RefAck.D
|
|
TimeoutA.D
|
|
TimeoutB.D
|
|
cnt/RefCnt<1>.D
|
|
cnt/RefCnt<2>.D
|
|
cnt/RefCnt<3>.D
|
|
cnt/RefCnt<4>.D
|
|
cnt/RefCnt<5>.D
|
|
cnt/RefCnt<6>.D
|
|
cnt/RefCnt<7>.D
|
|
cnt/RefDone.D
|
|
cnt/TimeoutBPre.D
|
|
cs/nOverlay0.D
|
|
cs/nOverlay1.CE
|
|
cs/nOverlay1.D
|
|
fsb/BERR0r.D
|
|
fsb/BERR1r.D
|
|
fsb/Ready0r.D
|
|
fsb/Ready1r.D 11.0
|
|
fsb/Ready2r.D
|
|
fsb/VPA.D 11.4
|
|
iobs/Clear1.D 10.0 10.0
|
|
iobs/IOL1.CE 10.0
|
|
iobs/IORW1.D 10.0 10.0 11.0 11.0
|
|
iobs/IOReady.D 10.0 10.0 10.0 10.0
|
|
iobs/IOU1.CE 10.0
|
|
iobs/Load1.D 10.0 10.0 10.0
|
|
iobs/Once.D 11.4 11.0 10.0
|
|
iobs/PS_FSM_FFd1.D 10.0 10.0 10.0
|
|
iobs/PS_FSM_FFd2.D 10.0 10.0 11.0 11.0
|
|
nADoutLE1.D 10.0 10.0
|
|
nBR_IOB.CE
|
|
nCAS.D
|
|
nDTACK_FSB.D 11.4
|
|
ram/BACTr.D
|
|
ram/Once.D
|
|
ram/RAMDIS1.D
|
|
ram/RAMDIS2.D
|
|
ram/RAMReady.D
|
|
ram/RASEL.D
|
|
ram/RS_FSM_FFd1.D
|
|
ram/RS_FSM_FFd2.D
|
|
ram/RS_FSM_FFd3.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: CLK_FSB)
|
|
|
|
\ From n n n r r r r r r r
|
|
\ A B D a a a a a a a
|
|
\ D R T m m m m m m m
|
|
\ o _ A / / / / / / /
|
|
\ u I C B O R R R R R
|
|
\ t O K A n A A A S S
|
|
\ L B _ C c M M S _ _
|
|
\ E . F T e D R E F F
|
|
\ 1 Q S r . I e L S S
|
|
\ . B . Q S a . M M
|
|
\ Q . Q 2 d Q _ _
|
|
\ Q . y F F
|
|
\ Q . F F
|
|
\ Q d d
|
|
\ 1 2
|
|
\ . .
|
|
\ Q Q
|
|
\
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0S.D
|
|
BERR_IOBS.D 10.0
|
|
IOL0.CE
|
|
IOL0.D 10.0
|
|
IOREQ.D 11.0
|
|
IORW0.D 11.4
|
|
IOU0.CE
|
|
IOU0.D 10.0
|
|
IPL2r1.D
|
|
RESDone.CE
|
|
RESr1.D
|
|
RESr2.D
|
|
RefAck.D 10.0 10.0
|
|
TimeoutA.D
|
|
TimeoutB.D
|
|
cnt/RefCnt<1>.D
|
|
cnt/RefCnt<2>.D
|
|
cnt/RefCnt<3>.D
|
|
cnt/RefCnt<4>.D
|
|
cnt/RefCnt<5>.D
|
|
cnt/RefCnt<6>.D
|
|
cnt/RefCnt<7>.D
|
|
cnt/RefDone.D
|
|
cnt/TimeoutBPre.D
|
|
cs/nOverlay0.D
|
|
cs/nOverlay1.CE
|
|
cs/nOverlay1.D
|
|
fsb/BERR0r.D
|
|
fsb/BERR1r.D
|
|
fsb/Ready0r.D 10.0
|
|
fsb/Ready1r.D 11.0
|
|
fsb/Ready2r.D
|
|
fsb/VPA.D 11.0 11.4 20.1
|
|
iobs/Clear1.D 10.0
|
|
iobs/IOL1.CE
|
|
iobs/IORW1.D 10.0
|
|
iobs/IOReady.D 10.0
|
|
iobs/IOU1.CE
|
|
iobs/Load1.D 10.0
|
|
iobs/Once.D 11.0
|
|
iobs/PS_FSM_FFd1.D
|
|
iobs/PS_FSM_FFd2.D 11.0
|
|
nADoutLE1.D 10.0
|
|
nBR_IOB.CE
|
|
nCAS.D 10.0
|
|
nDTACK_FSB.D 11.0 11.4 11.4 20.1
|
|
ram/BACTr.D
|
|
ram/Once.D 10.0 10.0 10.0
|
|
ram/RAMDIS1.D 11.0 11.0 11.4 11.0
|
|
ram/RAMDIS2.D 11.0 11.0 11.0 11.0
|
|
ram/RAMReady.D 11.0 11.0 11.0 11.0
|
|
ram/RASEL.D 11.0 11.4 11.4 11.4
|
|
ram/RS_FSM_FFd1.D 10.0 10.0 10.0
|
|
ram/RS_FSM_FFd2.D 11.0 11.4 11.4
|
|
ram/RS_FSM_FFd3.D 10.0 11.0 11.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: CLK_FSB)
|
|
|
|
\ From r
|
|
\ a
|
|
\ m
|
|
\ /
|
|
\ R
|
|
\ S
|
|
\ _
|
|
\ F
|
|
\ S
|
|
\ M
|
|
\ _
|
|
\ F
|
|
\ F
|
|
\ d
|
|
\ 3
|
|
\ .
|
|
\ Q
|
|
\
|
|
To \------
|
|
|
|
ALE0S.D
|
|
BERR_IOBS.D
|
|
IOL0.CE
|
|
IOL0.D
|
|
IOREQ.D
|
|
IORW0.D
|
|
IOU0.CE
|
|
IOU0.D
|
|
IPL2r1.D
|
|
RESDone.CE
|
|
RESr1.D
|
|
RESr2.D
|
|
RefAck.D
|
|
TimeoutA.D
|
|
TimeoutB.D
|
|
cnt/RefCnt<1>.D
|
|
cnt/RefCnt<2>.D
|
|
cnt/RefCnt<3>.D
|
|
cnt/RefCnt<4>.D
|
|
cnt/RefCnt<5>.D
|
|
cnt/RefCnt<6>.D
|
|
cnt/RefCnt<7>.D
|
|
cnt/RefDone.D
|
|
cnt/TimeoutBPre.D
|
|
cs/nOverlay0.D
|
|
cs/nOverlay1.CE
|
|
cs/nOverlay1.D
|
|
fsb/BERR0r.D
|
|
fsb/BERR1r.D
|
|
fsb/Ready0r.D
|
|
fsb/Ready1r.D
|
|
fsb/Ready2r.D
|
|
fsb/VPA.D
|
|
iobs/Clear1.D
|
|
iobs/IOL1.CE
|
|
iobs/IORW1.D
|
|
iobs/IOReady.D
|
|
iobs/IOU1.CE
|
|
iobs/Load1.D
|
|
iobs/Once.D
|
|
iobs/PS_FSM_FFd1.D
|
|
iobs/PS_FSM_FFd2.D
|
|
nADoutLE1.D
|
|
nBR_IOB.CE
|
|
nCAS.D
|
|
nDTACK_FSB.D
|
|
ram/BACTr.D
|
|
ram/Once.D 10.0
|
|
ram/RAMDIS1.D 11.0
|
|
ram/RAMDIS2.D 11.0
|
|
ram/RAMReady.D 11.0
|
|
ram/RASEL.D 11.0
|
|
ram/RS_FSM_FFd1.D 10.0
|
|
ram/RS_FSM_FFd2.D 11.4
|
|
ram/RS_FSM_FFd3.D 11.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: CLK2X_IOB)
|
|
|
|
\ From I I i i i i i i i i
|
|
\ O O o o o o o o o o
|
|
\ A B b b b b b b b b
|
|
\ C E m m m m m m m m
|
|
\ T R / / / / / / / /
|
|
\ . R B B B B D D E E
|
|
\ Q . E E G G T T S S
|
|
\ Q R R r r A A < <
|
|
\ R R 0 1 C C 0 1
|
|
\ r r . . K K > >
|
|
\ f r Q Q r r . .
|
|
\ . . f r Q Q
|
|
\ Q Q . .
|
|
\ Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0M.D
|
|
IOACT.D 10.0 10.0 11.0 11.0
|
|
IOBERR.D 11.0 11.0 11.0 11.0 11.0
|
|
iobm/BGr1.D 10.0
|
|
iobm/ES<0>.D 10.0 10.0
|
|
iobm/ES<1>.D 10.0 10.0
|
|
iobm/ES<2>.D 10.0 10.0
|
|
iobm/ES<3>.D 10.0 10.0
|
|
iobm/ES<4>.D 10.0 10.0
|
|
iobm/ETACK.D 10.0 10.0
|
|
iobm/IOS_FSM_FFd1.D
|
|
iobm/IOS_FSM_FFd2.D 10.0 10.0 10.0 10.0
|
|
iobm/IOS_FSM_FFd3.D
|
|
nAS_IOB.D
|
|
nAoutOE.D 10.0 10.0
|
|
nDinLE.D
|
|
nDoutOE.D
|
|
nLDS_IOB.D
|
|
nUDS_IOB.D
|
|
nVMA_IOB.D 10.0 10.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: CLK2X_IOB)
|
|
|
|
\ From i i i i i i i i i i
|
|
\ o o o o o o o o o o
|
|
\ b b b b b b b b b b
|
|
\ m m m m m m m m m m
|
|
\ / / / / / / / / / /
|
|
\ E E E E E I I I I R
|
|
\ S S S T r O O O O E
|
|
\ < < < A 2 R S S S S
|
|
\ 2 3 4 C . E _ _ _ r
|
|
\ > > > K Q Q F F F f
|
|
\ . . . . r S S S .
|
|
\ Q Q Q Q . M M M Q
|
|
\ Q _ _ _
|
|
\ F F F
|
|
\ F F F
|
|
\ d d d
|
|
\ 1 2 3
|
|
\ . . .
|
|
\ Q Q Q
|
|
To \------------------------------------------------------------
|
|
|
|
ALE0M.D 10.0 10.0 10.0 10.0
|
|
IOACT.D 10.0 10.0 11.0 10.0 11.0 11.0
|
|
IOBERR.D 10.0 11.0 11.0 11.0 11.0
|
|
iobm/BGr1.D
|
|
iobm/ES<0>.D 10.0 10.0 10.0 10.0
|
|
iobm/ES<1>.D 10.0
|
|
iobm/ES<2>.D 10.0 10.0 10.0 10.0
|
|
iobm/ES<3>.D 10.0 10.0 10.0
|
|
iobm/ES<4>.D 10.0 10.0 10.0 10.0
|
|
iobm/ETACK.D 10.0 10.0 10.0
|
|
iobm/IOS_FSM_FFd1.D 10.0 10.0 10.0
|
|
iobm/IOS_FSM_FFd2.D 10.0 10.0 10.0 10.0 10.0
|
|
iobm/IOS_FSM_FFd3.D 10.0 10.0 10.0 10.0
|
|
nAS_IOB.D 10.0 10.0 10.0
|
|
nAoutOE.D
|
|
nDinLE.D 10.0 10.0
|
|
nDoutOE.D 10.0 10.0
|
|
nLDS_IOB.D 10.0 10.0 10.0
|
|
nUDS_IOB.D 10.0 10.0 10.0
|
|
nVMA_IOB.D 10.0 10.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: CLK2X_IOB)
|
|
|
|
\ From i i i n n n
|
|
\ o o o A A V
|
|
\ b b b S o M
|
|
\ m m m _ u A
|
|
\ / / / I t _
|
|
\ R V V O O I
|
|
\ E P P B E O
|
|
\ S A A . . B
|
|
\ r r r Q Q .
|
|
\ r f r Q
|
|
\ . . .
|
|
\ Q Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------
|
|
|
|
ALE0M.D 10.0
|
|
IOACT.D 11.0 10.0
|
|
IOBERR.D 11.0
|
|
iobm/BGr1.D
|
|
iobm/ES<0>.D
|
|
iobm/ES<1>.D
|
|
iobm/ES<2>.D
|
|
iobm/ES<3>.D
|
|
iobm/ES<4>.D
|
|
iobm/ETACK.D 10.0
|
|
iobm/IOS_FSM_FFd1.D
|
|
iobm/IOS_FSM_FFd2.D 10.0
|
|
iobm/IOS_FSM_FFd3.D 10.0
|
|
nAS_IOB.D
|
|
nAoutOE.D 10.0 10.0
|
|
nDinLE.D
|
|
nDoutOE.D
|
|
nLDS_IOB.D
|
|
nUDS_IOB.D
|
|
nVMA_IOB.D 10.0 10.0 10.0
|
|
|
|
Path Type Definition:
|
|
|
|
Pad to Pad (tPD) - Reports pad to pad paths that start
|
|
at input pads and end at output pads.
|
|
Paths are not traced through
|
|
registers.
|
|
|
|
Clock Pad to Output Pad (tCO) - Reports paths that start at input
|
|
pads trace through clock inputs of
|
|
registers and end at output pads.
|
|
Paths are not traced through PRE/CLR
|
|
inputs of registers.
|
|
|
|
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
|
|
to clock at pad. Data path starts at
|
|
an input pad and ends at register
|
|
(Fast Input Register for tSUF) D/T
|
|
input. Clock path starts at input pad
|
|
and ends at the register clock input.
|
|
Paths are not traced through
|
|
registers. Pin-to-pin setup
|
|
requirement is not reported or
|
|
guaranteed for product-term clocks
|
|
derived from macrocell feedback
|
|
signals.
|
|
|
|
Clock to Setup (tCYC) - Register to register cycle time.
|
|
Include source register tCO and
|
|
destination register tSU. Note that
|
|
when the computed Maximum Clock Speed
|
|
is limited by tCYC it is computed
|
|
assuming that all registers are
|
|
rising-edge sensitive.
|
|
|