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<title>CPLD Timing Report (Text)</title><PRE><FONT FACE="Courier New", monotype><p align=left><b>CPLD Timing Report (Text)</b></p><b><center>Mon Mar 28 09:30:32 2022</center></b><br><hr><br> Performance Summary Report<br> --------------------------<br><br>Design: WarpSE<br>Device: XC95144XL-10-TQ100<br>Speed File: Version 3.0<br>Program: Timing Report Generator: version P.20131013<br>Date: Mon Mar 28 09:28:06 2022<br><br>Timing Constraint Summary:<br><br>TS_CLK_IOB=PERIOD:CLK_IOB:142.857nS:HIGH:71.428nS N/A<br>TS_CLK_FSB=PERIOD:CLK_FSB:40.000nS:HIGH:20.000nS Met<br>TS_CLK2X_IOB=PERIOD:CLK2X_IOB:66.666nS:HIGH:33.333nS Met<br><br>Performance Summary:<br><br>Pad to Pad (tPD) : 11.0ns (1 macrocell levels)<br>Pad 'A_FSB<11>' to Pad 'RA<1>' <br><br>Clock net 'CLK_IOB' path delays:<br><br>Setup to Clock at the Pad (tSU) : 6.5ns (0 macrocell levels)<br>Data signal 'E_IOB' to DFF D input Pin at 'iobm/Er.D'<br>Clock pad 'CLK_IOB' (GCK)<br><br> Minimum Clock Period: 9.0ns<br> Maximum Internal Clock Speed: 111.1Mhz<br> (Limited by Clock Pulse Width)<br><br>Clock net 'CLK_FSB' path delays:<br><br>Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)<br>Clock Pad 'CLK_FSB' to Output Pad 'RA<1>' (GCK)<br><br>Clock to Setup (tCYC) : 20.1ns (2 macrocell levels)<br>Clock to Q, net 'cs/nOverlay1.Q' to DFF Setup(D) at 'fsb/VPA.D' (GCK)<br>Target FF drives output net 'fsb/VPA'<br><br>Setup to Clock at the Pad (tSU) : 16.6ns (1 macrocell levels)<br>Data signal 'A_FSB<23>' to DFF D input Pin at 'fsb/VPA.D'<br>Clock pad 'CLK_FSB' (GCK)<br><br> Minimum Clock Period: 20.1ns<br> Maximum Internal Clock Speed: 49.7Mhz<br> (Limited by Cycle Time)<br><br>Clock net 'CLK2X_IOB' path delays:<br><br>Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)<br>Clock Pad 'CLK2X_IOB' to Output Pad 'nVMA_IOB' (GCK)<br><br>Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)<br>Clock to Q, net 'iobm/IOS_FSM_FFd3.Q' to DFF Setup(D) at 'IOACT.D' (GCK)<br>Target FF drives output net 'IOACT'<br><br>Setup to Clock at the Pad (tSU) : 7.5ns (0 macrocell levels)<br>Data signal 'CLK_IOB' to DFF D input Pin at 'IOACT.D'<br>Clock pad 'CLK2X_IOB' (GCK)<br><br> Minimum Clock Period: 11.0ns<br> Maximum Internal Clock Speed: 90.9Mhz<br> (Limited by Cycle Time)<br><br>--------------------------------------------------------------------------------<br> Pad to Pad (tPD) (nsec)<br><br>\ From A A A A A A A A A A A<br> \ _ _ _ _ _ _ _ _ _ _ _<br> \ F F F F F F F F F F F<br> \ S S S S S S S S S S S<br> \ B B B B B B B B B B B<br> \ < < < < < < < < < < <<br> \ 1 1 1 1 1 1 1 1 1 1 1<br> \ 0 1 2 3 4 5 6 7 8 9 ><br> \ > > > > > > > > > > <br> To \------------------------------------------------------------------<br><br>CLK20EN <br>CLK25EN <br>RA<0> 10.0 10.0<br>RA<10> <br>RA<11> 10.0 <br>RA<1> 11.0 <br>RA<2> 11.0 <br>RA<3> 10.0 <br>RA<4> 11.0 <br>RA<5> 11.0 <br>RA<6> 10.0 <br>RA<7> 10.0 <br>RA<8> 10.0 <br>RA<9> 10.0 <br>nBERR_FSB <br>nDinOE <br>nOE <br>nRAMLWE <br>nRAMUWE <br>nRAS <br>nROMCS <br>nROMWE <br>nVPA_FSB <br><br>--------------------------------------------------------------------------------<br> Pad to Pad (tPD) (nsec)<br><br>\ From A A A A A A A A A A A<br> \ _ _ _ _ _ _ _ _ _ _ _<br> \ F F F F F F F F F F F<br> \ S S S S S S S S S S S<br> \ B B B B B B B B B B B<br> \ < < < < < < < < < < <<br> \ 2 2 2 2 2 3 4 5 6 7 8<br> \ 0 1 2 3 > > > > > > ><br> \ > > > > <br> To \------------------------------------------------------------------<br><br>CLK20EN <br>CLK25EN <br>RA<0> <br>RA<10> 10.0 <br>RA<11> <br>RA<1> 11.0 <br>RA<2> 11.0 <br>RA<3> 10.0 <br>RA<4> 11.0 <br>RA<5> 11.0 <br>RA<6> 10.0 <br>RA<7> 10.0<br>RA<8> 11.0 11.0 11.0 <br>RA<9> 10.0 <br>nBERR_FSB 11.0 11.0 11.0 11.0 <br>nDinOE 10.0 10.0 10.0 10.0 <br>nOE <br>nRAMLWE <br>nRAMUWE <br>nRAS 11.0 11.0 11.0 <br>nROMCS 11.0 11.0 11.0 11.0 <br>nROMWE <br>nVPA_FSB <br><br>--------------------------------------------------------------------------------<br> Pad to Pad (tPD) (nsec)<br><br>\ From A S S n n n n<br> \ _ W W A L U W<br> \ F < < S D D E<br> \ S 0 1 _ S S _<br> \ B > > F _ _ F<br> \ < S F F S<br> \ 9 B S S B<br> \ > B B <br> \ <br> To \------------------------------------------<br><br>CLK20EN 10.0 <br>CLK25EN 10.0 <br>RA<0> <br>RA<10> <br>RA<11> <br>RA<1> <br>RA<2> <br>RA<3> <br>RA<4> <br>RA<5> <br>RA<6> <br>RA<7> <br>RA<8> 11.0 <br>RA<9> <br>nBERR_FSB 10.0 <br>nDinOE 10.0 10.0 10.0<br>nOE 10.0 10.0<br>nRAMLWE 10.0 10.0 10.0<br>nRAMUWE 11.0 11.0 11.0<br>nRAS 11.0 <br>nROMCS 11.0 <br>nROMWE 10.0 10.0<br>nVPA_FSB 10.0 <br><br>--------------------------------------------------------------------------------<br> Clock Pad to Output Pad (tCO) (nsec)<br><br>\ From C C<br> \ L L<br> \ K K<br> \ 2 _<br> \ X F<br> \ _ S<br> \ I B<br> \ O <br> \ B <br> \ <br> To \------------<br><br>RA<0> 13.5<br>RA<1> 14.5<br>RA<2> 14.5<br>RA<3> 13.5<br>RA<4> 14.5<br>RA<5> 14.5<br>RA<6> 13.5<br>RA<7> 13.5<br>RA<8> 14.5<br>RA<9> 13.5<br>nADoutLE0 13.5 13.5<br>nADoutLE1 5.8<br>nAS_IOB 14.5 <br>nAoutOE 5.8 <br>nBERR_FSB 14.5<br>nBR_IOB 5.8<br>nCAS 5.8<br>nDTACK_FSB 5.8<br>nDinLE 5.8 <br>nDoutOE 5.8 <br>nLDS_IOB 14.5 <br>nRAMLWE 13.5<br>nRAMUWE 14.5<br>nRAS 14.5<br>nROMCS 14.5<br>nUDS_IOB 14.5 <br>nVMA_IOB 14.5 <br>nVPA_FSB 13.5<br><br>--------------------------------------------------------------------------------<br> Setup to Clock at Pad (tSU or tSUF) (nsec)<br><br>\ From C C C<br> \ L L L<br> \ K K K<br> \ 2 _ _<br> \ X F I<br> \ _ S O<br> \ I B B<br> \ O <br> \ B <br> \ <br> To \------------------<br><br>A_FSB<10> 7.9 <br>A_FSB<11> 7.9 <br>A_FSB<12> 7.9 <br>A_FSB<13> 7.9 <br>A_FSB<14> 7.9 <br>A_FSB<15> 7.9 <br>A_FSB<16> 7.9 <br>A_FSB<17> 7.9 <br>A_FSB<18> 7.9 <br>A_FSB<19> 7.9 <br>A_FSB<20> 15.6 <br>A_FSB<21> 16.6 <br>A_FSB<22> 16.6 <br>A_FSB<23> 16.6 <br>A_FSB<8> 7.9 <br>A_FSB<9> 7.9 <br>CLK_IOB 7.5 <br>E_IOB 6.5<br>SW<1> 7.9 <br>nAS_FSB 15.6 <br>nBERR_IOB 7.5 <br>nBG_IOB 6.5 <br>nDTACK_IOB 6.5 <br>nIPL2 6.5 <br>nLDS_FSB 6.5 <br>nRES 6.5 6.5 <br>nUDS_FSB 6.5 <br>nVPA_IOB 6.5 <br>nWE_FSB 7.9 <br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK_FSB)<br><br>\ From B I I I R R R R R T<br> \ E O P P E E E E e i<br> \ R R L L S S S S f m<br> \ R W 2 2 D r r r A e<br> \ _ 0 r r o 0 1 2 c o<br> \ I . 0 1 n . . . k u<br> \ O Q . . e Q Q Q . t<br> \ B Q Q . Q A<br> \ S Q .<br> \ . Q<br> \ Q <br> \ <br> \ <br> \ <br> \ <br> \ <br> \ <br> \ <br> To \------------------------------------------------------------<br><br>ALE0S.D <br>BERR_IOBS.D 10.0 <br>IOL0.CE <br>IOL0.D <br>IOREQ.D <br>IORW0.D 11.4 <br>IOU0.CE <br>IOU0.D <br>IPL2r1.D 10.0 <br>RESDone.CE 10.0 10.0 10.0 <br>RESr1.D 10.0 <br>RESr2.D 10.0 <br>RefAck.D <br>TimeoutA.D 10.0<br>TimeoutB.D <br>cnt/RefCnt<1>.D <br>cnt/RefCnt<2>.D <br>cnt/RefCnt<3>.D <br>cnt/RefCnt<4>.D <br>cnt/RefCnt<5>.D <br>cnt/RefCnt<6>.D <br>cnt/RefCnt<7>.D <br>cnt/RefDone.D 10.0 <br>cnt/TimeoutBPre.D <br>cs/nOverlay0.D <br>cs/nOverlay1.CE <br>cs/nOverlay1.D <br>fsb/BERR0r.D <br>fsb/BERR1r.D 10.0 <br>fsb/Ready0r.D <br>fsb/Ready1r.D <br>fsb/Ready2r.D 11.0<br>fsb/VPA.D 11.4 11.4<br>iobs/Clear1.D <br>iobs/IOL1.CE <br>iobs/IORW1.D <br>iobs/IOReady.D <br>iobs/IOU1.CE <br>iobs/Load1.D <br>iobs/Once.D <br>iobs/PS_FSM_FFd1.D <br>iobs/PS_FSM_FFd2.D <br>nADoutLE1.D <br>nBR_IOB.CE 10.0 10.0 10.0 10.0 10.0 10.0 <br>nCAS.D <br>nDTACK_FSB.D 11.4 11.4<br>ram/BACTr.D <br>ram/Once.D <br>ram/RAMDIS1.D <br>ram/RAMDIS2.D <br>ram/RAMReady.D <br>ram/RASEL.D <br>ram/RS_FSM_FFd1.D <br>ram/RS_FSM_FFd2.D <br>ram/RS_FSM_FFd3.D <br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK_FSB)<br><br>\ From T c c c c c c c c c<br> \ i n n n n n n n n n<br> \ m t t t t t t t t t<br> \ e / / / / / / / / /<br> \ o R R R R R R R R R<br> \ u e e e e e e e e e<br> \ t f f f f f f f f f<br> \ B C C C C C C C C D<br> \ . n n n n n n n n o<br> \ Q t t t t t t t t n<br> \ < < < < < < < < e<br> \ 0 1 2 3 4 5 6 7 .<br> \ > > > > > > > > Q<br> \ . . . . . . . . <br> \ Q Q Q Q Q Q Q Q <br> \ <br> \ <br> \ <br> To \------------------------------------------------------------<br><br>ALE0S.D <br>BERR_IOBS.D <br>IOL0.CE <br>IOL0.D <br>IOREQ.D <br>IORW0.D <br>IOU0.CE <br>IOU0.D <br>IPL2r1.D <br>RESDone.CE <br>RESr1.D <br>RESr2.D <br>RefAck.D <br>TimeoutA.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 <br>TimeoutB.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 <br>cnt/RefCnt<1>.D 10.0 <br>cnt/RefCnt<2>.D 10.0 10.0 <br>cnt/RefCnt<3>.D 10.0 10.0 10.0 <br>cnt/RefCnt<4>.D 10.0 10.0 10.0 10.0 <br>cnt/RefCnt<5>.D 10.0 10.0 10.0 10.0 10.0 <br>cnt/RefCnt<6>.D 10.0 10.0 10.0 10.0 10.0 10.0 <br>cnt/RefCnt<7>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 <br>cnt/RefDone.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0<br>cnt/TimeoutBPre.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 <br>cs/nOverlay0.D <br>cs/nOverlay1.CE <br>cs/nOverlay1.D <br>fsb/BERR0r.D 10.0 <br>fsb/BERR1r.D <br>fsb/Ready0r.D <br>fsb/Ready1r.D <br>fsb/Ready2r.D <br>fsb/VPA.D 19.1 <br>iobs/Clear1.D <br>iobs/IOL1.CE <br>iobs/IORW1.D <br>iobs/IOReady.D <br>iobs/IOU1.CE <br>iobs/Load1.D <br>iobs/Once.D <br>iobs/PS_FSM_FFd1.D <br>iobs/PS_FSM_FFd2.D <br>nADoutLE1.D <br>nBR_IOB.CE <br>nCAS.D <br>nDTACK_FSB.D 19.1 <br>ram/BACTr.D <br>ram/Once.D <br>ram/RAMDIS1.D 11.4 11.4 11.4 11.4<br>ram/RAMDIS2.D 11.0 11.0 11.0 11.0<br>ram/RAMReady.D 11.4 11.4 11.4 11.4<br>ram/RASEL.D 11.4 11.4 11.4 11.4<br>ram/RS_FSM_FFd1.D <br>ram/RS_FSM_FFd2.D 11.4 11.4 11.4 11.4<br>ram/RS_FSM_FFd3.D 11.0 11.0 11.0 11.0<br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK_FSB)<br><br>\ From c c c f f f f f f f<br> \ n s s s s s s s s s<br> \ t / / b b b b b b b<br> \ / n n / / / / / / /<br> \ T O O A B B R R R V<br> \ i v v S E E e e e P<br> \ m e e r R R a a a A<br> \ e r r f R R d d d .<br> \ o l l . 0 1 y y y Q<br> \ u a a Q r r 0 1 2 <br> \ t y y . . r r r <br> \ B 0 1 Q Q . . . <br> \ P . . Q Q Q <br> \ r Q Q <br> \ e <br> \ . <br> \ Q <br> \ <br> To \------------------------------------------------------------<br><br>ALE0S.D <br>BERR_IOBS.D 10.0 <br>IOL0.CE <br>IOL0.D <br>IOREQ.D 11.0 10.0 <br>IORW0.D 10.0 11.0 <br>IOU0.CE <br>IOU0.D <br>IPL2r1.D <br>RESDone.CE <br>RESr1.D <br>RESr2.D <br>RefAck.D <br>TimeoutA.D 10.0 <br>TimeoutB.D 10.0 10.0 <br>cnt/RefCnt<1>.D <br>cnt/RefCnt<2>.D <br>cnt/RefCnt<3>.D <br>cnt/RefCnt<4>.D <br>cnt/RefCnt<5>.D <br>cnt/RefCnt<6>.D <br>cnt/RefCnt<7>.D <br>cnt/RefDone.D <br>cnt/TimeoutBPre.D 10.0 10.0 <br>cs/nOverlay0.D 10.0 10.0 <br>cs/nOverlay1.CE 10.0 <br>cs/nOverlay1.D 10.0 <br>fsb/BERR0r.D 10.0 10.0 <br>fsb/BERR1r.D 10.0 10.0 <br>fsb/Ready0r.D 10.0 10.0 10.0 <br>fsb/Ready1r.D 11.0 10.0 11.0 <br>fsb/Ready2r.D 11.0 11.0 11.0 <br>fsb/VPA.D 20.1 19.1 11.4 11.4 20.1 11.4 11.4 11.4<br>iobs/Clear1.D <br>iobs/IOL1.CE <br>iobs/IORW1.D 11.4 11.0 <br>iobs/IOReady.D 10.0 <br>iobs/IOU1.CE <br>iobs/Load1.D 11.0 10.0 <br>iobs/Once.D 11.4 10.0 <br>iobs/PS_FSM_FFd1.D <br>iobs/PS_FSM_FFd2.D 11.0 10.0 <br>nADoutLE1.D <br>nBR_IOB.CE <br>nCAS.D <br>nDTACK_FSB.D 20.1 11.0 11.4 11.4 20.1 11.4 11.4 <br>ram/BACTr.D 10.0 <br>ram/Once.D 10.0 10.0 <br>ram/RAMDIS1.D 11.4 11.0 <br>ram/RAMDIS2.D 11.0 11.0 <br>ram/RAMReady.D 11.0 11.0 <br>ram/RASEL.D 11.4 11.4 <br>ram/RS_FSM_FFd1.D 10.0 10.0 <br>ram/RS_FSM_FFd2.D 11.4 11.4 <br>ram/RS_FSM_FFd3.D 11.0 11.0 <br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK_FSB)<br><br>\ From i i i i i i i i i i<br> \ o o o o o o o o o o<br> \ b b b b b b b b b b<br> \ s s s s s s s s s s<br> \ / / / / / / / / / /<br> \ C I I I I I L O P P<br> \ l O O O O O o n S S<br> \ e A L R R U a c _ _<br> \ a C 1 W e 1 d e F F<br> \ r T . 1 a . 1 . S S<br> \ 1 r Q . d Q . Q M M<br> \ . . Q y Q _ _<br> \ Q Q . F F<br> \ Q F F<br> \ d d<br> \ 1 2<br> \ . .<br> \ Q Q<br> To \------------------------------------------------------------<br><br>ALE0S.D 10.0 10.0<br>BERR_IOBS.D 10.0 10.0 10.0<br>IOL0.CE 10.0 10.0<br>IOL0.D 10.0 <br>IOREQ.D 10.0 10.0 10.0 11.0<br>IORW0.D 11.0 11.4 11.4 11.4<br>IOU0.CE 10.0 10.0<br>IOU0.D 10.0 <br>IPL2r1.D <br>RESDone.CE <br>RESr1.D <br>RESr2.D <br>RefAck.D <br>TimeoutA.D <br>TimeoutB.D <br>cnt/RefCnt<1>.D <br>cnt/RefCnt<2>.D <br>cnt/RefCnt<3>.D <br>cnt/RefCnt<4>.D <br>cnt/RefCnt<5>.D <br>cnt/RefCnt<6>.D <br>cnt/RefCnt<7>.D <br>cnt/RefDone.D <br>cnt/TimeoutBPre.D <br>cs/nOverlay0.D <br>cs/nOverlay1.CE <br>cs/nOverlay1.D <br>fsb/BERR0r.D <br>fsb/BERR1r.D <br>fsb/Ready0r.D <br>fsb/Ready1r.D 11.0 <br>fsb/Ready2r.D <br>fsb/VPA.D 11.4 <br>iobs/Clear1.D 10.0 10.0<br>iobs/IOL1.CE 10.0 <br>iobs/IORW1.D 10.0 10.0 11.0 11.0<br>iobs/IOReady.D 10.0 10.0 10.0 10.0<br>iobs/IOU1.CE 10.0 <br>iobs/Load1.D 10.0 10.0 10.0<br>iobs/Once.D 11.4 11.0 10.0<br>iobs/PS_FSM_FFd1.D 10.0 10.0 10.0<br>iobs/PS_FSM_FFd2.D 10.0 10.0 11.0 11.0<br>nADoutLE1.D 10.0 10.0 <br>nBR_IOB.CE <br>nCAS.D <br>nDTACK_FSB.D 11.4 <br>ram/BACTr.D <br>ram/Once.D <br>ram/RAMDIS1.D <br>ram/RAMDIS2.D <br>ram/RAMReady.D <br>ram/RASEL.D <br>ram/RS_FSM_FFd1.D <br>ram/RS_FSM_FFd2.D <br>ram/RS_FSM_FFd3.D <br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK_FSB)<br><br>\ From n n n r r r r r r r<br> \ A B D a a a a a a a<br> \ D R T m m m m m m m<br> \ o _ A / / / / / / /<br> \ u I C B O R R R R R<br> \ t O K A n A A A S S<br> \ L B _ C c M M S _ _<br> \ E . F T e D R E F F<br> \ 1 Q S r . I e L S S<br> \ . B . Q S a . M M<br> \ Q . Q 2 d Q _ _<br> \ Q . y F F<br> \ Q . F F<br> \ Q d d<br> \ 1 2<br> \ . .<br> \ Q Q<br> \ <br> To \------------------------------------------------------------<br><br>ALE0S.D <br>BERR_IOBS.D 10.0 <br>IOL0.CE <br>IOL0.D 10.0 <br>IOREQ.D 11.0 <br>IORW0.D 11.4 <br>IOU0.CE <br>IOU0.D 10.0 <br>IPL2r1.D <br>RESDone.CE <br>RESr1.D <br>RESr2.D <br>RefAck.D 10.0 10.0<br>TimeoutA.D <br>TimeoutB.D <br>cnt/RefCnt<1>.D <br>cnt/RefCnt<2>.D <br>cnt/RefCnt<3>.D <br>cnt/RefCnt<4>.D <br>cnt/RefCnt<5>.D <br>cnt/RefCnt<6>.D <br>cnt/RefCnt<7>.D <br>cnt/RefDone.D <br>cnt/TimeoutBPre.D <br>cs/nOverlay0.D <br>cs/nOverlay1.CE <br>cs/nOverlay1.D <br>fsb/BERR0r.D <br>fsb/BERR1r.D <br>fsb/Ready0r.D 10.0 <br>fsb/Ready1r.D 11.0 <br>fsb/Ready2r.D <br>fsb/VPA.D 11.0 11.4 20.1 <br>iobs/Clear1.D 10.0 <br>iobs/IOL1.CE <br>iobs/IORW1.D 10.0 <br>iobs/IOReady.D 10.0 <br>iobs/IOU1.CE <br>iobs/Load1.D 10.0 <br>iobs/Once.D 11.0 <br>iobs/PS_FSM_FFd1.D <br>iobs/PS_FSM_FFd2.D 11.0 <br>nADoutLE1.D 10.0 <br>nBR_IOB.CE <br>nCAS.D 10.0 <br>nDTACK_FSB.D 11.0 11.4 11.4 20.1 <br>ram/BACTr.D <br>ram/Once.D 10.0 10.0 10.0<br>ram/RAMDIS1.D 11.0 11.0 11.4 11.0<br>ram/RAMDIS2.D 11.0 11.0 11.0 11.0<br>ram/RAMReady.D 11.0 11.0 11.0 11.0<br>ram/RASEL.D 11.0 11.4 11.4 11.4<br>ram/RS_FSM_FFd1.D 10.0 10.0 10.0<br>ram/RS_FSM_FFd2.D 11.0 11.4 11.4<br>ram/RS_FSM_FFd3.D 10.0 11.0 11.0<br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK_FSB)<br><br>\ From r<br> \ a<br> \ m<br> \ /<br> \ R<br> \ S<br> \ _<br> \ F<br> \ S<br> \ M<br> \ _<br> \ F<br> \ F<br> \ d<br> \ 3<br> \ .<br> \ Q<br> \ <br> To \------<br><br>ALE0S.D <br>BERR_IOBS.D <br>IOL0.CE <br>IOL0.D <br>IOREQ.D <br>IORW0.D <br>IOU0.CE <br>IOU0.D <br>IPL2r1.D <br>RESDone.CE <br>RESr1.D <br>RESr2.D <br>RefAck.D <br>TimeoutA.D <br>TimeoutB.D <br>cnt/RefCnt<1>.D <br>cnt/RefCnt<2>.D <br>cnt/RefCnt<3>.D <br>cnt/RefCnt<4>.D <br>cnt/RefCnt<5>.D <br>cnt/RefCnt<6>.D <br>cnt/RefCnt<7>.D <br>cnt/RefDone.D <br>cnt/TimeoutBPre.D <br>cs/nOverlay0.D <br>cs/nOverlay1.CE <br>cs/nOverlay1.D <br>fsb/BERR0r.D <br>fsb/BERR1r.D <br>fsb/Ready0r.D <br>fsb/Ready1r.D <br>fsb/Ready2r.D <br>fsb/VPA.D <br>iobs/Clear1.D <br>iobs/IOL1.CE <br>iobs/IORW1.D <br>iobs/IOReady.D <br>iobs/IOU1.CE <br>iobs/Load1.D <br>iobs/Once.D <br>iobs/PS_FSM_FFd1.D <br>iobs/PS_FSM_FFd2.D <br>nADoutLE1.D <br>nBR_IOB.CE <br>nCAS.D <br>nDTACK_FSB.D <br>ram/BACTr.D <br>ram/Once.D 10.0<br>ram/RAMDIS1.D 11.0<br>ram/RAMDIS2.D 11.0<br>ram/RAMReady.D 11.0<br>ram/RASEL.D 11.0<br>ram/RS_FSM_FFd1.D 10.0<br>ram/RS_FSM_FFd2.D 11.4<br>ram/RS_FSM_FFd3.D 11.0<br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK2X_IOB)<br><br>\ From I I i i i i i i i i<br> \ O O o o o o o o o o<br> \ A B b b b b b b b b<br> \ C E m m m m m m m m<br> \ T R / / / / / / / /<br> \ . R B B B B D D E E<br> \ Q . E E G G T T S S<br> \ Q R R r r A A < <<br> \ R R 0 1 C C 0 1<br> \ r r . . K K > ><br> \ f r Q Q r r . .<br> \ . . f r Q Q<br> \ Q Q . . <br> \ Q Q <br> \ <br> \ <br> \ <br> \ <br> \ <br> To \------------------------------------------------------------<br><br>ALE0M.D <br>IOACT.D 10.0 10.0 11.0 11.0 <br>IOBERR.D 11.0 11.0 11.0 11.0 11.0 <br>iobm/BGr1.D 10.0 <br>iobm/ES<0>.D 10.0 10.0<br>iobm/ES<1>.D 10.0 10.0<br>iobm/ES<2>.D 10.0 10.0<br>iobm/ES<3>.D 10.0 10.0<br>iobm/ES<4>.D 10.0 10.0<br>iobm/ETACK.D 10.0 10.0<br>iobm/IOS_FSM_FFd1.D <br>iobm/IOS_FSM_FFd2.D 10.0 10.0 10.0 10.0 <br>iobm/IOS_FSM_FFd3.D <br>nAS_IOB.D <br>nAoutOE.D 10.0 10.0 <br>nDinLE.D <br>nDoutOE.D <br>nLDS_IOB.D <br>nUDS_IOB.D <br>nVMA_IOB.D 10.0 10.0 10.0<br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK2X_IOB)<br><br>\ From i i i i i i i i i i<br> \ o o o o o o o o o o<br> \ b b b b b b b b b b<br> \ m m m m m m m m m m<br> \ / / / / / / / / / /<br> \ E E E E E I I I I R<br> \ S S S T r O O O O E<br> \ < < < A 2 R S S S S<br> \ 2 3 4 C . E _ _ _ r<br> \ > > > K Q Q F F F f<br> \ . . . . r S S S .<br> \ Q Q Q Q . M M M Q<br> \ Q _ _ _ <br> \ F F F <br> \ F F F <br> \ d d d <br> \ 1 2 3 <br> \ . . . <br> \ Q Q Q <br> To \------------------------------------------------------------<br><br>ALE0M.D 10.0 10.0 10.0 10.0 <br>IOACT.D 10.0 10.0 11.0 10.0 11.0 11.0<br>IOBERR.D 10.0 11.0 11.0 11.0 11.0<br>iobm/BGr1.D <br>iobm/ES<0>.D 10.0 10.0 10.0 10.0 <br>iobm/ES<1>.D 10.0 <br>iobm/ES<2>.D 10.0 10.0 10.0 10.0 <br>iobm/ES<3>.D 10.0 10.0 10.0 <br>iobm/ES<4>.D 10.0 10.0 10.0 10.0 <br>iobm/ETACK.D 10.0 10.0 10.0 <br>iobm/IOS_FSM_FFd1.D 10.0 10.0 10.0 <br>iobm/IOS_FSM_FFd2.D 10.0 10.0 10.0 10.0 10.0<br>iobm/IOS_FSM_FFd3.D 10.0 10.0 10.0 10.0 <br>nAS_IOB.D 10.0 10.0 10.0 <br>nAoutOE.D <br>nDinLE.D 10.0 10.0 <br>nDoutOE.D 10.0 10.0 <br>nLDS_IOB.D 10.0 10.0 10.0 <br>nUDS_IOB.D 10.0 10.0 10.0 <br>nVMA_IOB.D 10.0 10.0 10.0 <br><br>--------------------------------------------------------------------------------<br> Clock to Setup (tCYC) (nsec)<br> (Clock: CLK2X_IOB)<br><br>\ From i i i n n n<br> \ o o o A A V<br> \ b b b S o M<br> \ m m m _ u A<br> \ / / / I t _<br> \ R V V O O I<br> \ E P P B E O<br> \ S A A . . B<br> \ r r r Q Q .<br> \ r f r Q<br> \ . . . <br> \ Q Q Q <br> \ <br> \ <br> \ <br> \ <br> \ <br> \ <br> \ <br> To \------------------------------------<br><br>ALE0M.D 10.0 <br>IOACT.D 11.0 10.0 <br>IOBERR.D 11.0 <br>iobm/BGr1.D <br>iobm/ES<0>.D <br>iobm/ES<1>.D <br>iobm/ES<2>.D <br>iobm/ES<3>.D <br>iobm/ES<4>.D <br>iobm/ETACK.D 10.0<br>iobm/IOS_FSM_FFd1.D <br>iobm/IOS_FSM_FFd2.D 10.0 <br>iobm/IOS_FSM_FFd3.D 10.0 <br>nAS_IOB.D <br>nAoutOE.D 10.0 10.0 <br>nDinLE.D <br>nDoutOE.D <br>nLDS_IOB.D <br>nUDS_IOB.D <br>nVMA_IOB.D 10.0 10.0 10.0<br><br>Path Type Definition: <br><br>Pad to Pad (tPD) - Reports pad to pad paths that start <br> at input pads and end at output pads. <br> Paths are not traced through <br> registers. <br><br>Clock Pad to Output Pad (tCO) - Reports paths that start at input <br> pads trace through clock inputs of <br> registers and end at output pads. <br> Paths are not traced through PRE/CLR <br> inputs of registers. <br><br>Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data <br> to clock at pad. Data path starts at <br> an input pad and ends at register <br> (Fast Input Register for tSUF) D/T <br> input. Clock path starts at input pad <br> and ends at the register clock input. <br> Paths are not traced through <br> registers. Pin-to-pin setup <br> requirement is not reported or <br> guaranteed for product-term clocks <br> derived from macrocell feedback <br> signals. <br><br>Clock to Setup (tCYC) - Register to register cycle time. <br> Include source register tCO and <br> destination register tSU. Note that <br> when the computed Maximum Clock Speed <br> is limited by tCYC it is computed <br> assuming that all registers are <br> rising-edge sensitive. <br><br></PRE></FONT> |