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31 lines
549 B
Verilog
31 lines
549 B
Verilog
module CFG(
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input [23:20] A,
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inout GA23,
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inout GA22,
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inout GA21,
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inout GA20,
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output SlowdownIOWriteGate,
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input DBG0_ROMWS,
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input DBG1_RAMWS,
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input DBG4_IOWS,
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output ROMWS,
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output RAMWS,
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output IOWS);
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assign GA23 = 1'bZ;
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wire GA23Gate =
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(A[23:20]==4'h6) ||
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(A[23:20]==4'h7 && A[19:16]!=4'hF) ||
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(A[23:20]==4'h5 && !A[19]);
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assign GA22 = ) ? 1'b0 : A[23];
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assign GA21 = 1'bZ;
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assign GA20 = 1'bZ;
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assign SlowdownIOWriteGate = 1;
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assign ROMWS = DBG0_ROMWS;
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assign RAMWS = DBG1_RAMWS;
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assign IOWS = DBG4_IOWS;
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endmodule
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