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15 lines
225 B
Verilog
15 lines
225 B
Verilog
module SET(
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input CLK,
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input nPOR,
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input BACT,
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input A1,
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input SetCSWR,
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output reg SetSndSlow);
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always @(posedge CLK) begin
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if (!nPOR) SetSndSlow <= 1;
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else if (BACT && SetCSWR) SetSndSlow <= A1;
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end
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endmodule
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