1319 lines
68 KiB
Plaintext
1319 lines
68 KiB
Plaintext
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: MXSE Date: 2- 7-2022, 0:19AM
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Device Used: XC95144XL-10-TQ100
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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105/144 ( 73%) 429 /720 ( 60%) 234/432 ( 54%) 80 /144 ( 56%) 67 /81 ( 83%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 18/54 22/90 11/11*
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FB2 3/18 2/54 2/90 8/10
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FB3 6/18 38/54 81/90 10/10*
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FB4 11/18 36/54 81/90 10/10*
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FB5 13/18 33/54 81/90 8/10
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FB6 18/18* 34/54 62/90 10/10*
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FB7 18/18* 38/54 63/90 6/10
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FB8 18/18* 35/54 37/90 4/10
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----- ----- ----- -----
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105/144 234/432 429/720 67/81
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'CLK2X_IOB' mapped onto global clock net GCK1.
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Signal 'CLK_IOB' mapped onto global clock net GCK2.
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Signal 'CLK_FSB' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 32 32 | I/O : 61 73
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Output : 32 32 | GCK/IO : 3 3
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Bidirectional : 0 0 | GTS/IO : 3 4
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GCK : 3 3 | GSR/IO : 0 1
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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Total 67 67
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** Power Data **
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There are 105 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'MXSE.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK2X_IOB' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_FSB' based upon the LOC
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constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'CLK_IOB' based upon the LOC
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constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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************************* Summary of Mapped Logic ************************
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** 32 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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nDTACK_FSB 22 33 FB3_9 28 I/O O STD FAST RESET
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nROMWE 1 2 FB3_17 34 I/O O STD FAST
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nAoutOE 1 0 FB4_2 87 I/O O STD FAST
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nDoutOE 2 4 FB4_5 89 I/O O STD FAST RESET
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nDinOE 2 6 FB4_6 90 I/O O STD FAST
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nBERR_FSB 3 9 FB4_9 92 I/O O STD FAST
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nVPA_FSB 1 2 FB4_11 93 I/O O STD FAST
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nROMCS 2 5 FB5_2 35 I/O O STD FAST
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nCAS 1 1 FB5_5 36 I/O O STD FAST RESET
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nOE 1 2 FB5_6 37 I/O O STD FAST
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RA<4> 2 3 FB5_9 40 I/O O STD FAST
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RA<3> 2 3 FB5_11 41 I/O O STD FAST
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RA<5> 2 3 FB5_12 42 I/O O STD FAST
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RA<2> 2 3 FB5_14 43 I/O O STD FAST
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RA<6> 2 3 FB5_15 46 I/O O STD FAST
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nVMA_IOB 2 9 FB6_2 74 I/O O STD FAST RESET
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nLDS_IOB 4 6 FB6_9 79 I/O O STD FAST RESET
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nUDS_IOB 4 6 FB6_11 80 I/O O STD FAST RESET
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nAS_IOB 2 4 FB6_12 81 I/O O STD FAST RESET
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nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
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nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
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nDinLE 2 3 FB6_17 86 I/O O STD FAST RESET
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RA<1> 2 3 FB7_2 50 I/O O STD FAST
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RA<7> 2 3 FB7_5 52 I/O O STD FAST
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RA<0> 2 3 FB7_6 53 I/O O STD FAST
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RA<8> 2 3 FB7_8 54 I/O O STD FAST
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RA<10> 1 1 FB7_9 55 I/O O STD FAST
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RA<9> 2 3 FB7_11 56 I/O O STD FAST
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RA<11> 1 1 FB8_2 63 I/O O STD FAST
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nRAS 3 8 FB8_5 64 I/O O STD FAST
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nRAMLWE 1 5 FB8_6 65 I/O O STD FAST
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nRAMUWE 1 5 FB8_8 66 I/O O STD FAST
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** 73 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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iobm/VPArr 1 1 FB1_1 STD RESET
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iobm/VPArf 1 1 FB1_2 STD RESET
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iobm/RESrr 1 1 FB1_3 STD RESET
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iobm/RESrf 1 1 FB1_4 STD RESET
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iobm/IOREQr 1 1 FB1_5 STD RESET
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iobm/Er2 1 1 FB1_6 STD RESET
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iobm/DTACKrr 1 1 FB1_7 STD RESET
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iobm/DTACKrf 1 1 FB1_8 STD RESET
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iobm/BERRrr 1 1 FB1_9 STD RESET
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iobm/BERRrf 1 1 FB1_10 STD RESET
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fsb/ASrf 1 1 FB1_11 STD RESET
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cnt/RefCnt<1> 1 1 FB1_12 STD RESET
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RefAck 1 2 FB1_13 STD RESET
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$OpTx$$OpTx$FX_DC$355_INV$439 1 2 FB1_14 STD
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iobs/IOU1 2 2 FB1_15 STD RESET
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iobs/IOL1 2 2 FB1_16 STD RESET
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iobm/IOS_FSM_FFd2 2 4 FB1_17 STD RESET
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iobm/IOS_FSM_FFd1 2 4 FB1_18 STD RESET
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iobs/IOACTr 1 1 FB2_16 STD RESET
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iobm/Er 1 1 FB2_17 STD RESET
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cnt/RefCnt<0> 0 0 FB2_18 STD RESET
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fsb/VPA 25 31 FB3_2 STD RESET
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fsb/Ready1r 7 17 FB3_5 STD RESET
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fsb/Ready2r 9 22 FB3_14 STD RESET
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iobs/Once 17 18 FB3_16 STD RESET
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ram/RAMDIS1 18 15 FB4_3 STD RESET
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ram/RAMReady 16 15 FB4_8 STD RESET
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fsb/BERR0r 3 8 FB4_10 STD RESET
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iobs/Load1 14 18 FB4_12 STD RESET
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iobs/Clear1 1 3 FB4_14 STD RESET
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ram/RASEL 20 15 FB4_16 STD RESET
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iobs/PS_FSM_FFd2 14 19 FB5_4 STD RESET
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iobs/IORW1 16 19 FB5_8 STD RESET
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IOREQ 14 19 FB5_13 STD RESET
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ram/Once 5 10 FB5_16 STD RESET
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IORW0 18 20 FB5_18 STD RESET
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iobm/ETACK 1 6 FB6_1 STD RESET
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ALE0M 2 5 FB6_3 STD RESET
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iobm/ES<3> 3 6 FB6_4 STD RESET
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iobm/ES<1> 3 4 FB6_5 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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iobm/ES<0> 3 7 FB6_6 STD RESET
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iobm/IOS_FSM_FFd4 4 6 FB6_7 STD RESET
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iobm/ES<4> 4 7 FB6_8 STD RESET
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iobm/IOS_FSM_FFd3 5 10 FB6_10 STD RESET
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iobm/ES<2> 5 7 FB6_13 STD RESET
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IOACT 6 13 FB6_16 STD RESET
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IOBERR 9 14 FB6_18 STD RESET
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ram/RS_FSM_FFd2 13 14 FB7_1 STD RESET
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cnt/TimeoutBPre 3 11 FB7_3 STD RESET
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cnt/RefCnt<4> 1 4 FB7_4 STD RESET
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fsb/Ready0r 3 8 FB7_7 STD RESET
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cs/nOverlay0 3 8 FB7_10 STD RESET
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TimeoutB 3 12 FB7_12 STD RESET
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cnt/RefCnt<5> 1 5 FB7_13 STD RESET
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ram/RS_FSM_FFd1 5 10 FB7_14 STD RESET
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ram/RAMDIS2 7 15 FB7_15 STD RESET
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ram/RS_FSM_FFd3 11 14 FB7_16 STD RESET
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cnt/RefCnt<7> 1 7 FB7_17 STD RESET
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cnt/RefCnt<6> 1 6 FB7_18 STD RESET
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ram/BACTr 1 2 FB8_1 STD RESET
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cnt/RefCnt<3> 1 3 FB8_3 STD RESET
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cnt/RefCnt<2> 1 2 FB8_4 STD RESET
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ALE0S 1 2 FB8_7 STD RESET
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iobs/PS_FSM_FFd1 2 3 FB8_9 STD RESET
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fsb/BERR1r 2 4 FB8_10 STD RESET
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cs/nOverlay1 2 3 FB8_11 STD RESET
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cnt/RefDone 2 10 FB8_12 STD RESET
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$OpTx$FX_DC$360 2 2 FB8_13 STD
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TimeoutA 3 10 FB8_14 STD RESET
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IOU0 3 5 FB8_15 STD RESET
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IOL0 3 5 FB8_16 STD RESET
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iobs/IOReady 4 8 FB8_17 STD RESET
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BERR_IOBS 4 8 FB8_18 STD RESET
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** 35 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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A_FSB<13> FB1_2 11 I/O I
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A_FSB<14> FB1_3 12 I/O I
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A_FSB<15> FB1_5 13 I/O I
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A_FSB<16> FB1_6 14 I/O I
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A_FSB<17> FB1_8 15 I/O I
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A_FSB<18> FB1_9 16 I/O I
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A_FSB<19> FB1_11 17 I/O I
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A_FSB<20> FB1_12 18 I/O I
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A_FSB<21> FB1_14 19 I/O I
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A_FSB<22> FB1_15 20 I/O I
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CLK2X_IOB FB1_17 22 GCK/I/O GCK
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A_FSB<5> FB2_6 2 GTS/I/O I
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A_FSB<6> FB2_8 3 GTS/I/O I
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A_FSB<7> FB2_9 4 GTS/I/O I
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A_FSB<8> FB2_11 6 I/O I
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A_FSB<9> FB2_12 7 I/O I
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A_FSB<10> FB2_14 8 I/O I
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A_FSB<11> FB2_15 9 I/O I
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A_FSB<12> FB2_17 10 I/O I
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CLK_IOB FB3_2 23 GCK/I/O GCK/I
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A_FSB<23> FB3_5 24 I/O I
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E_IOB FB3_6 25 I/O I
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CLK_FSB FB3_8 27 GCK/I/O GCK
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nWE_FSB FB3_11 29 I/O I
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nLDS_FSB FB3_12 30 I/O I
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nAS_FSB FB3_14 32 I/O I
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nUDS_FSB FB3_15 33 I/O I
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nRES FB4_8 91 I/O I
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A_FSB<1> FB4_12 94 I/O I
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A_FSB<2> FB4_14 95 I/O I
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A_FSB<3> FB4_15 96 I/O I
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A_FSB<4> FB4_17 97 I/O I
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nBERR_IOB FB6_5 76 I/O I
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nVPA_IOB FB6_6 77 I/O I
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nDTACK_IOB FB6_8 78 I/O I
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Legend:
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Pin No. - ~ - User Assigned
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************************** Function Block Details ************************
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X - Signal used as input to the macrocell logic.
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Pin No. - ~ - User Assigned
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*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 18/36
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Number of signals used by logic mapping into function block: 18
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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iobm/VPArr 1 0 0 4 FB1_1 (b) (b)
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iobm/VPArf 1 0 0 4 FB1_2 11 I/O I
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iobm/RESrr 1 0 0 4 FB1_3 12 I/O I
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iobm/RESrf 1 0 0 4 FB1_4 (b) (b)
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iobm/IOREQr 1 0 0 4 FB1_5 13 I/O I
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iobm/Er2 1 0 0 4 FB1_6 14 I/O I
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iobm/DTACKrr 1 0 0 4 FB1_7 (b) (b)
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iobm/DTACKrf 1 0 0 4 FB1_8 15 I/O I
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iobm/BERRrr 1 0 0 4 FB1_9 16 I/O I
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iobm/BERRrf 1 0 0 4 FB1_10 (b) (b)
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fsb/ASrf 1 0 0 4 FB1_11 17 I/O I
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cnt/RefCnt<1> 1 0 0 4 FB1_12 18 I/O I
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RefAck 1 0 0 4 FB1_13 (b) (b)
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$OpTx$$OpTx$FX_DC$355_INV$439
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1 0 0 4 FB1_14 19 I/O I
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iobs/IOU1 2 0 0 3 FB1_15 20 I/O I
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iobs/IOL1 2 0 0 3 FB1_16 (b) (b)
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iobm/IOS_FSM_FFd2 2 0 0 3 FB1_17 22 GCK/I/O GCK
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iobm/IOS_FSM_FFd1 2 0 0 3 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: IOREQ 7: iobm/IOS_FSM_FFd3 13: nLDS_FSB
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2: cnt/RefCnt<0> 8: iobm/IOS_FSM_FFd4 14: nRES
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3: fsb/ASrf 9: iobs/Load1 15: nUDS_FSB
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4: iobm/Er 10: nAS_FSB 16: nVPA_IOB
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5: iobm/IOS_FSM_FFd1 11: nBERR_IOB 17: ram/RS_FSM_FFd1
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6: iobm/IOS_FSM_FFd2 12: nDTACK_IOB 18: ram/RS_FSM_FFd2
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Signal 1 2 3 4 FB
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Name 0----+----0----+----0----+----0----+----0 Inputs
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iobm/VPArr ...............X........................ 1
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iobm/VPArf ...............X........................ 1
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iobm/RESrr .............X.......................... 1
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iobm/RESrf .............X.......................... 1
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iobm/IOREQr X....................................... 1
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iobm/Er2 ...X.................................... 1
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iobm/DTACKrr ...........X............................ 1
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iobm/DTACKrf ...........X............................ 1
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iobm/BERRrr ..........X............................. 1
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iobm/BERRrf ..........X............................. 1
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fsb/ASrf .........X.............................. 1
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cnt/RefCnt<1> .X...................................... 1
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RefAck ................XX...................... 2
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$OpTx$$OpTx$FX_DC$355_INV$439
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..X......X.............................. 2
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iobs/IOU1 ........X.....X......................... 2
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iobs/IOL1 ........X...X........................... 2
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iobm/IOS_FSM_FFd2 ....XXXX................................ 4
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iobm/IOS_FSM_FFd1 ....XXXX................................ 4
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0----+----1----+----2----+----3----+----4
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0 0 0 0
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*********************************** FB2 ***********************************
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Number of function block inputs used/remaining: 2/52
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Number of signals used by logic mapping into function block: 2
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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(unused) 0 0 0 5 FB2_1 (b)
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(unused) 0 0 0 5 FB2_2 99 GSR/I/O
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(unused) 0 0 0 5 FB2_3 (b)
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(unused) 0 0 0 5 FB2_4 (b)
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(unused) 0 0 0 5 FB2_5 1 GTS/I/O
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(unused) 0 0 0 5 FB2_6 2 GTS/I/O I
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(unused) 0 0 0 5 FB2_7 (b)
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(unused) 0 0 0 5 FB2_8 3 GTS/I/O I
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(unused) 0 0 0 5 FB2_9 4 GTS/I/O I
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(unused) 0 0 0 5 FB2_10 (b)
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(unused) 0 0 0 5 FB2_11 6 I/O I
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(unused) 0 0 0 5 FB2_12 7 I/O I
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(unused) 0 0 0 5 FB2_13 (b)
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(unused) 0 0 0 5 FB2_14 8 I/O I
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(unused) 0 0 0 5 FB2_15 9 I/O I
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iobs/IOACTr 1 0 0 4 FB2_16 (b) (b)
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iobm/Er 1 0 0 4 FB2_17 10 I/O I
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cnt/RefCnt<0> 0 0 0 5 FB2_18 (b) (b)
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Signals Used by Logic in Function Block
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1: E_IOB 2: IOACT
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Signal 1 2 3 4 FB
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Name 0----+----0----+----0----+----0----+----0 Inputs
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iobs/IOACTr .X...................................... 1
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iobm/Er X....................................... 1
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cnt/RefCnt<0> ........................................ 0
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0----+----1----+----2----+----3----+----4
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0 0 0 0
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*********************************** FB3 ***********************************
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Number of function block inputs used/remaining: 38/16
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Number of signals used by logic mapping into function block: 38
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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(unused) 0 0 \/5 0 FB3_1 (b) (b)
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fsb/VPA 25 20<- 0 0 FB3_2 23 GCK/I/O GCK/I
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(unused) 0 0 /\5 0 FB3_3 (b) (b)
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(unused) 0 0 /\5 0 FB3_4 (b) (b)
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fsb/Ready1r 7 2<- 0 0 FB3_5 24 I/O I
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(unused) 0 0 /\2 3 FB3_6 25 I/O I
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(unused) 0 0 \/5 0 FB3_7 (b) (b)
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(unused) 0 0 \/5 0 FB3_8 27 GCK/I/O GCK
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nDTACK_FSB 22 17<- 0 0 FB3_9 28 I/O O
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(unused) 0 0 /\5 0 FB3_10 (b) (b)
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(unused) 0 0 /\2 3 FB3_11 29 I/O I
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(unused) 0 0 \/2 3 FB3_12 30 I/O I
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(unused) 0 0 \/5 0 FB3_13 (b) (b)
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fsb/Ready2r 9 7<- \/3 0 FB3_14 32 I/O I
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(unused) 0 0 \/5 0 FB3_15 33 I/O I
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iobs/Once 17 12<- 0 0 FB3_16 (b) (b)
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nROMWE 1 0 /\4 0 FB3_17 34 I/O O
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(unused) 0 0 \/5 0 FB3_18 (b) (b)
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Signals Used by Logic in Function Block
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1: $OpTx$$OpTx$FX_DC$355_INV$439 14: A_FSB<21> 27: fsb/Ready1r
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2: $OpTx$FX_DC$360 15: A_FSB<22> 28: fsb/Ready2r
|
||
3: A_FSB<10> 16: A_FSB<23> 29: fsb/VPA
|
||
4: A_FSB<11> 17: A_FSB<8> 30: iobs/IOReady
|
||
5: A_FSB<12> 18: A_FSB<9> 31: iobs/Once
|
||
6: A_FSB<13> 19: BERR_IOBS 32: iobs/PS_FSM_FFd1
|
||
7: A_FSB<14> 20: TimeoutA 33: iobs/PS_FSM_FFd2
|
||
8: A_FSB<15> 21: TimeoutB 34: nADoutLE1
|
||
9: A_FSB<16> 22: cs/nOverlay1 35: nAS_FSB
|
||
10: A_FSB<17> 23: fsb/ASrf 36: nDTACK_FSB
|
||
11: A_FSB<18> 24: fsb/BERR0r 37: nWE_FSB
|
||
12: A_FSB<19> 25: fsb/BERR1r 38: ram/RAMReady
|
||
13: A_FSB<20> 26: fsb/Ready0r
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
fsb/VPA X.XXXXXXXXXXXXXXXXXXXX.XXXXXXX...X..XX.. 31
|
||
fsb/Ready1r .....XX.XXXXXXXX.....XX...X..X...XX.X... 17
|
||
nDTACK_FSB .XXXXXXXXXXXXXXXXXXXXXXXXXXX.X...XXXXX.. 33
|
||
fsb/Ready2r ..XXXXXXXXXXXXXXXX.X.XX....X......X.X... 22
|
||
iobs/Once .....XX.XXXXXXXX.....XX.......XXXXX.X... 18
|
||
nROMWE ..................................X.X... 2
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB4 ***********************************
|
||
Number of function block inputs used/remaining: 36/18
|
||
Number of signals used by logic mapping into function block: 36
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
(unused) 0 0 0 5 FB4_1 (b) (b)
|
||
nAoutOE 1 1<- \/5 0 FB4_2 87 I/O O
|
||
ram/RAMDIS1 18 13<- 0 0 FB4_3 (b) (b)
|
||
(unused) 0 0 /\5 0 FB4_4 (b) (b)
|
||
nDoutOE 2 0 /\3 0 FB4_5 89 I/O O
|
||
nDinOE 2 0 \/3 0 FB4_6 90 I/O O
|
||
(unused) 0 0 \/5 0 FB4_7 (b) (b)
|
||
ram/RAMReady 16 11<- 0 0 FB4_8 91 I/O I
|
||
nBERR_FSB 3 1<- /\3 0 FB4_9 92 I/O O
|
||
fsb/BERR0r 3 0 /\1 1 FB4_10 (b) (b)
|
||
nVPA_FSB 1 0 \/4 0 FB4_11 93 I/O O
|
||
iobs/Load1 14 9<- 0 0 FB4_12 94 I/O I
|
||
(unused) 0 0 /\5 0 FB4_13 (b) (b)
|
||
iobs/Clear1 1 0 \/4 0 FB4_14 95 I/O I
|
||
(unused) 0 0 \/5 0 FB4_15 96 I/O I
|
||
ram/RASEL 20 15<- 0 0 FB4_16 (b) (b)
|
||
(unused) 0 0 /\5 0 FB4_17 97 I/O I
|
||
(unused) 0 0 /\1 4 FB4_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<13> 13: TimeoutB 25: iobm/IOS_FSM_FFd4
|
||
2: A_FSB<14> 14: cnt/RefCnt<5> 26: iobs/Once
|
||
3: A_FSB<16> 15: cnt/RefCnt<6> 27: iobs/PS_FSM_FFd1
|
||
4: A_FSB<17> 16: cnt/RefCnt<7> 28: iobs/PS_FSM_FFd2
|
||
5: A_FSB<18> 17: cnt/RefDone 29: nADoutLE1
|
||
6: A_FSB<19> 18: cs/nOverlay1 30: nAS_FSB
|
||
7: A_FSB<20> 19: fsb/ASrf 31: nWE_FSB
|
||
8: A_FSB<21> 20: fsb/BERR0r 32: ram/BACTr
|
||
9: A_FSB<22> 21: fsb/BERR1r 33: ram/Once
|
||
10: A_FSB<23> 22: fsb/VPA 34: ram/RS_FSM_FFd1
|
||
11: BERR_IOBS 23: iobm/IOS_FSM_FFd2 35: ram/RS_FSM_FFd2
|
||
12: IORW0 24: iobm/IOS_FSM_FFd3 36: ram/RS_FSM_FFd3
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
nAoutOE ........................................ 0
|
||
ram/RAMDIS1 .......XXX...XXXXXX..........X.XXXXX.... 15
|
||
nDoutOE ...........X..........XXX............... 4
|
||
nDinOE ......XXXX...................XX......... 6
|
||
ram/RAMReady .......XXX...XXXXXX..........X.XXXXX.... 15
|
||
nBERR_FSB ......XXXXX.X......XX........X.......... 9
|
||
fsb/BERR0r ......XXXX..X.....XX.........X.......... 8
|
||
nVPA_FSB .....................X.......X.......... 2
|
||
iobs/Load1 XXXXXXXXXX.......XX......XXXXXX......... 18
|
||
iobs/Clear1 ..........................XXX........... 3
|
||
ram/RASEL .......XXX...XXXXXX..........X.XXXXX.... 15
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB5 ***********************************
|
||
Number of function block inputs used/remaining: 33/21
|
||
Number of signals used by logic mapping into function block: 33
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
(unused) 0 0 /\5 0 FB5_1 (b) (b)
|
||
nROMCS 2 0 /\3 0 FB5_2 35 I/O O
|
||
(unused) 0 0 \/5 0 FB5_3 (b) (b)
|
||
iobs/PS_FSM_FFd2 14 9<- 0 0 FB5_4 (b) (b)
|
||
nCAS 1 0 /\4 0 FB5_5 36 I/O O
|
||
nOE 1 0 \/1 3 FB5_6 37 I/O O
|
||
(unused) 0 0 \/5 0 FB5_7 (b) (b)
|
||
iobs/IORW1 16 11<- 0 0 FB5_8 39 I/O (b)
|
||
RA<4> 2 2<- /\5 0 FB5_9 40 I/O O
|
||
(unused) 0 0 /\2 3 FB5_10 (b) (b)
|
||
RA<3> 2 0 \/2 1 FB5_11 41 I/O O
|
||
RA<5> 2 2<- \/5 0 FB5_12 42 I/O O
|
||
IOREQ 14 9<- 0 0 FB5_13 (b) (b)
|
||
RA<2> 2 1<- /\4 0 FB5_14 43 I/O O
|
||
RA<6> 2 0 /\1 2 FB5_15 46 I/O O
|
||
ram/Once 5 0 0 0 FB5_16 (b) (b)
|
||
(unused) 0 0 \/5 0 FB5_17 49 I/O (b)
|
||
IORW0 18 13<- 0 0 FB5_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<12> 12: A_FSB<23> 23: iobs/Once
|
||
2: A_FSB<13> 13: A_FSB<3> 24: iobs/PS_FSM_FFd1
|
||
3: A_FSB<14> 14: A_FSB<4> 25: iobs/PS_FSM_FFd2
|
||
4: A_FSB<15> 15: A_FSB<5> 26: nADoutLE1
|
||
5: A_FSB<16> 16: A_FSB<6> 27: nAS_FSB
|
||
6: A_FSB<17> 17: A_FSB<7> 28: nWE_FSB
|
||
7: A_FSB<18> 18: IORW0 29: ram/Once
|
||
8: A_FSB<19> 19: cs/nOverlay1 30: ram/RASEL
|
||
9: A_FSB<20> 20: fsb/ASrf 31: ram/RS_FSM_FFd1
|
||
10: A_FSB<21> 21: iobs/IOACTr 32: ram/RS_FSM_FFd2
|
||
11: A_FSB<22> 22: iobs/IORW1 33: ram/RS_FSM_FFd3
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
nROMCS ........XXXX......X..................... 5
|
||
iobs/PS_FSM_FFd2 .XX.XXXXXXXX......XXX.XXXXXX............ 19
|
||
nCAS .............................X.......... 1
|
||
nOE ..........................XX............ 2
|
||
iobs/IORW1 .XX.XXXXXXXX......XX.XXXXXXX............ 19
|
||
RA<4> ..X...........X..............X.......... 3
|
||
RA<3> .X...........X...............X.......... 3
|
||
RA<5> ...X...........X.............X.......... 3
|
||
IOREQ .XX.XXXXXXXX......XXX.XXXXXX............ 19
|
||
RA<2> X...........X................X.......... 3
|
||
RA<6> ....X...........X............X.......... 3
|
||
ram/Once .........XXX......XX......X.X.XXX....... 10
|
||
IORW0 .XX.XXXXXXXX.....XXX.XXXXXXX............ 20
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB6 ***********************************
|
||
Number of function block inputs used/remaining: 34/20
|
||
Number of signals used by logic mapping into function block: 34
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
iobm/ETACK 1 0 /\1 3 FB6_1 (b) (b)
|
||
nVMA_IOB 2 0 0 3 FB6_2 74 I/O O
|
||
ALE0M 2 0 0 3 FB6_3 (b) (b)
|
||
iobm/ES<3> 3 0 0 2 FB6_4 (b) (b)
|
||
iobm/ES<1> 3 0 0 2 FB6_5 76 I/O I
|
||
iobm/ES<0> 3 0 0 2 FB6_6 77 I/O I
|
||
iobm/IOS_FSM_FFd4 4 0 0 1 FB6_7 (b) (b)
|
||
iobm/ES<4> 4 0 0 1 FB6_8 78 I/O I
|
||
nLDS_IOB 4 0 0 1 FB6_9 79 I/O O
|
||
iobm/IOS_FSM_FFd3 5 0 0 0 FB6_10 (b) (b)
|
||
nUDS_IOB 4 0 0 1 FB6_11 80 I/O O
|
||
nAS_IOB 2 0 0 3 FB6_12 81 I/O O
|
||
iobm/ES<2> 5 0 0 0 FB6_13 (b) (b)
|
||
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
|
||
nADoutLE0 1 0 \/1 3 FB6_15 85 I/O O
|
||
IOACT 6 1<- 0 0 FB6_16 (b) (b)
|
||
nDinLE 2 0 \/3 0 FB6_17 86 I/O O
|
||
IOBERR 9 4<- 0 0 FB6_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: ALE0M 13: iobm/ES<0> 24: iobm/IOS_FSM_FFd3
|
||
2: ALE0S 14: iobm/ES<1> 25: iobm/IOS_FSM_FFd4
|
||
3: CLK_IOB 15: iobm/ES<2> 26: iobm/RESrf
|
||
4: IOACT 16: iobm/ES<3> 27: iobm/RESrr
|
||
5: IOBERR 17: iobm/ES<4> 28: iobm/VPArf
|
||
6: IOL0 18: iobm/ETACK 29: iobm/VPArr
|
||
7: IORW0 19: iobm/Er 30: iobs/Clear1
|
||
8: IOU0 20: iobm/Er2 31: iobs/Load1
|
||
9: iobm/BERRrf 21: iobm/IOREQr 32: nADoutLE1
|
||
10: iobm/BERRrr 22: iobm/IOS_FSM_FFd1 33: nBERR_IOB
|
||
11: iobm/DTACKrf 23: iobm/IOS_FSM_FFd2 34: nVMA_IOB
|
||
12: iobm/DTACKrr
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
iobm/ETACK ............XXXXX................X...... 6
|
||
nVMA_IOB ...X........XXXXX..........XX....X...... 9
|
||
ALE0M ....................XXXXX............... 5
|
||
iobm/ES<3> ............XXXX..XX.................... 6
|
||
iobm/ES<1> ............XX....XX.................... 4
|
||
iobm/ES<0> ............XXXXX.XX.................... 7
|
||
iobm/IOS_FSM_FFd4 ..X.................XXXXX............... 6
|
||
iobm/ES<4> ............XXXXX.XX.................... 7
|
||
nLDS_IOB .....XX..............XXXX............... 6
|
||
iobm/IOS_FSM_FFd3 ..X.....XXXX.....X.....XXXX............. 10
|
||
nUDS_IOB ......XX.............XXXX............... 6
|
||
nAS_IOB .....................XXXX............... 4
|
||
iobm/ES<2> ............XXXXX.XX.................... 7
|
||
nADoutLE1 .............................XXX........ 3
|
||
nADoutLE0 XX...................................... 2
|
||
IOACT ..X.....XXXX.....X..XXXXXXX............. 13
|
||
nDinLE .....................X.XX............... 3
|
||
IOBERR ..X.X...XXXX.....X...XXXXXX.....X....... 14
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB7 ***********************************
|
||
Number of function block inputs used/remaining: 38/16
|
||
Number of signals used by logic mapping into function block: 38
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
ram/RS_FSM_FFd2 13 8<- 0 0 FB7_1 (b) (b)
|
||
RA<1> 2 1<- /\4 0 FB7_2 50 I/O O
|
||
cnt/TimeoutBPre 3 0 /\1 1 FB7_3 (b) (b)
|
||
cnt/RefCnt<4> 1 0 0 4 FB7_4 (b) (b)
|
||
RA<7> 2 0 0 3 FB7_5 52 I/O O
|
||
RA<0> 2 0 0 3 FB7_6 53 I/O O
|
||
fsb/Ready0r 3 0 0 2 FB7_7 (b) (b)
|
||
RA<8> 2 0 0 3 FB7_8 54 I/O O
|
||
RA<10> 1 0 0 4 FB7_9 55 I/O O
|
||
cs/nOverlay0 3 0 0 2 FB7_10 (b) (b)
|
||
RA<9> 2 0 0 3 FB7_11 56 I/O O
|
||
TimeoutB 3 0 0 2 FB7_12 58 I/O (b)
|
||
cnt/RefCnt<5> 1 0 \/4 0 FB7_13 (b) (b)
|
||
ram/RS_FSM_FFd1 5 4<- \/4 0 FB7_14 59 I/O (b)
|
||
ram/RAMDIS2 7 4<- \/2 0 FB7_15 60 I/O (b)
|
||
ram/RS_FSM_FFd3 11 6<- 0 0 FB7_16 (b) (b)
|
||
cnt/RefCnt<7> 1 0 /\4 0 FB7_17 61 I/O (b)
|
||
cnt/RefCnt<6> 1 0 \/4 0 FB7_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<10> 14: TimeoutB 27: fsb/ASrf
|
||
2: A_FSB<11> 15: cnt/RefCnt<0> 28: fsb/Ready0r
|
||
3: A_FSB<17> 16: cnt/RefCnt<1> 29: nAS_FSB
|
||
4: A_FSB<18> 17: cnt/RefCnt<2> 30: nRES
|
||
5: A_FSB<19> 18: cnt/RefCnt<3> 31: ram/BACTr
|
||
6: A_FSB<1> 19: cnt/RefCnt<4> 32: ram/Once
|
||
7: A_FSB<20> 20: cnt/RefCnt<5> 33: ram/RAMDIS2
|
||
8: A_FSB<21> 21: cnt/RefCnt<6> 34: ram/RAMReady
|
||
9: A_FSB<22> 22: cnt/RefCnt<7> 35: ram/RASEL
|
||
10: A_FSB<23> 23: cnt/RefDone 36: ram/RS_FSM_FFd1
|
||
11: A_FSB<2> 24: cnt/TimeoutBPre 37: ram/RS_FSM_FFd2
|
||
12: A_FSB<8> 25: cs/nOverlay0 38: ram/RS_FSM_FFd3
|
||
13: A_FSB<9> 26: cs/nOverlay1
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
ram/RS_FSM_FFd2 .......XXX.........XXXX..XX.X.X....XXX.. 14
|
||
RA<1> .X........X.......................X..... 3
|
||
cnt/TimeoutBPre ..............XXXXXXXX.X..X.X........... 11
|
||
cnt/RefCnt<4> ..............XXXX...................... 4
|
||
RA<7> ..X........X......................X..... 3
|
||
RA<0> X....X............................X..... 3
|
||
fsb/Ready0r .......XXX...............XXXX....X...... 8
|
||
RA<8> ...X........X.....................X..... 3
|
||
RA<10> .......X................................ 1
|
||
cs/nOverlay0 ......XXXX..............X.X.XX.......... 8
|
||
RA<9> ....X.X...........................X..... 3
|
||
TimeoutB .............XXXXXXXXX.X..X.X........... 12
|
||
cnt/RefCnt<5> ..............XXXXX..................... 5
|
||
ram/RS_FSM_FFd1 .......XXX...............XX.X..X...XXX.. 10
|
||
ram/RAMDIS2 .......XXX.........XXXX..XX.X..XX..XXX.. 15
|
||
ram/RS_FSM_FFd3 .......XXX.........XXXX..XX.X..X...XXX.. 14
|
||
cnt/RefCnt<7> ..............XXXXXXX................... 7
|
||
cnt/RefCnt<6> ..............XXXXXX.................... 6
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB8 ***********************************
|
||
Number of function block inputs used/remaining: 35/19
|
||
Number of signals used by logic mapping into function block: 35
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
ram/BACTr 1 0 0 4 FB8_1 (b) (b)
|
||
RA<11> 1 0 0 4 FB8_2 63 I/O O
|
||
cnt/RefCnt<3> 1 0 0 4 FB8_3 (b) (b)
|
||
cnt/RefCnt<2> 1 0 0 4 FB8_4 (b) (b)
|
||
nRAS 3 0 0 2 FB8_5 64 I/O O
|
||
nRAMLWE 1 0 0 4 FB8_6 65 I/O O
|
||
ALE0S 1 0 0 4 FB8_7 (b) (b)
|
||
nRAMUWE 1 0 0 4 FB8_8 66 I/O O
|
||
iobs/PS_FSM_FFd1 2 0 0 3 FB8_9 67 I/O (b)
|
||
fsb/BERR1r 2 0 0 3 FB8_10 (b) (b)
|
||
cs/nOverlay1 2 0 0 3 FB8_11 68 I/O (b)
|
||
cnt/RefDone 2 0 0 3 FB8_12 70 I/O (b)
|
||
$OpTx$FX_DC$360 2 0 0 3 FB8_13 (b) (b)
|
||
TimeoutA 3 0 0 2 FB8_14 71 I/O (b)
|
||
IOU0 3 0 0 2 FB8_15 72 I/O (b)
|
||
IOL0 3 0 0 2 FB8_16 (b) (b)
|
||
iobs/IOReady 4 0 0 1 FB8_17 73 I/O (b)
|
||
BERR_IOBS 4 0 0 1 FB8_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<19> 13: cnt/RefCnt<4> 25: iobs/IOU1
|
||
2: A_FSB<21> 14: cnt/RefCnt<5> 26: iobs/Once
|
||
3: A_FSB<22> 15: cnt/RefCnt<6> 27: iobs/PS_FSM_FFd1
|
||
4: A_FSB<23> 16: cnt/RefCnt<7> 28: iobs/PS_FSM_FFd2
|
||
5: BERR_IOBS 17: cnt/RefDone 29: nADoutLE1
|
||
6: IOBERR 18: cs/nOverlay0 30: nAS_FSB
|
||
7: RefAck 19: cs/nOverlay1 31: nLDS_FSB
|
||
8: TimeoutA 20: fsb/ASrf 32: nUDS_FSB
|
||
9: cnt/RefCnt<0> 21: fsb/BERR1r 33: nWE_FSB
|
||
10: cnt/RefCnt<1> 22: iobs/IOACTr 34: ram/RAMDIS1
|
||
11: cnt/RefCnt<2> 23: iobs/IOL1 35: ram/RAMDIS2
|
||
12: cnt/RefCnt<3> 24: iobs/IOReady
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
ram/BACTr ...................X.........X.......... 2
|
||
RA<11> X....................................... 1
|
||
cnt/RefCnt<3> ........XXX............................. 3
|
||
cnt/RefCnt<2> ........XX.............................. 2
|
||
nRAS .XXX..X...........X..........X...XX..... 8
|
||
nRAMLWE .............................XX.XXX..... 5
|
||
ALE0S ..........................XX............ 2
|
||
nRAMUWE .............................X.XXXX..... 5
|
||
iobs/PS_FSM_FFd1 .....................X....XX............ 3
|
||
fsb/BERR1r ....X..............XX........X.......... 4
|
||
cs/nOverlay1 .................X.X.........X.......... 3
|
||
cnt/RefDone ......X.XXXXXXXXX....................... 10
|
||
$OpTx$FX_DC$360 ..X...............X..................... 2
|
||
TimeoutA .......XXXXXXXX....X.........X.......... 10
|
||
IOU0 ........................X.XXX..X........ 5
|
||
IOL0 ......................X...XXX.X......... 5
|
||
iobs/IOReady .....X.............X.X.X.X.XXX.......... 8
|
||
BERR_IOBS ....XX.............X.X...X.XXX.......... 8
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
******************************* Equations ********************************
|
||
|
||
********** Mapped Logic **********
|
||
|
||
|
||
$OpTx$$OpTx$FX_DC$355_INV$439 <= (nAS_FSB AND NOT fsb/ASrf);
|
||
|
||
|
||
$OpTx$FX_DC$360 <= NOT (A_FSB(22)
|
||
XOR
|
||
$OpTx$FX_DC$360 <= NOT (cs/nOverlay1);
|
||
|
||
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
|
||
ALE0M_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
iobm/IOS_FSM_FFd1)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd2 AND NOT iobm/IOREQr));
|
||
|
||
FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,CLK_FSB,'0','0');
|
||
ALE0S_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||
|
||
FTCPE_BERR_IOBS: FTCPE port map (BERR_IOBS,BERR_IOBS_T,CLK_FSB,'0','0');
|
||
BERR_IOBS_T <= ((BERR_IOBS AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (iobs/Once AND BERR_IOBS AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
|
||
OR (iobs/Once AND NOT BERR_IOBS AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
|
||
OR (iobs/Once AND NOT BERR_IOBS AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/IOACTr AND IOBERR AND fsb/ASrf AND nADoutLE1));
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,CLK2X_IOB,'0','0');
|
||
IOACT_D <= ((NOT iobm/IOS_FSM_FFd4 AND iobm/IOS_FSM_FFd2 AND
|
||
iobm/IOS_FSM_FFd1 AND CLK_IOB AND iobm/RESrf AND iobm/RESrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
iobm/IOS_FSM_FFd1)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd2 AND NOT iobm/IOREQr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND iobm/IOS_FSM_FFd2 AND
|
||
iobm/IOS_FSM_FFd1 AND CLK_IOB AND iobm/ETACK)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND iobm/IOS_FSM_FFd2 AND
|
||
iobm/IOS_FSM_FFd1 AND CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND iobm/IOS_FSM_FFd2 AND
|
||
iobm/IOS_FSM_FFd1 AND CLK_IOB AND iobm/BERRrf AND iobm/BERRrr));
|
||
|
||
FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,CLK2X_IOB,'0','0');
|
||
IOBERR_T <= ((nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2 AND iobm/IOS_FSM_FFd1 AND CLK_IOB AND
|
||
IOBERR AND iobm/RESrf AND iobm/RESrr)
|
||
OR (nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2 AND iobm/IOS_FSM_FFd1 AND CLK_IOB AND
|
||
IOBERR AND iobm/ETACK)
|
||
OR (nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2 AND iobm/IOS_FSM_FFd1 AND CLK_IOB AND
|
||
IOBERR AND iobm/DTACKrf AND iobm/DTACKrr)
|
||
OR (nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2 AND iobm/IOS_FSM_FFd1 AND CLK_IOB AND
|
||
IOBERR AND iobm/BERRrf AND iobm/BERRrr)
|
||
OR (iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd2 AND NOT iobm/IOS_FSM_FFd1 AND IOBERR)
|
||
OR (NOT nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND CLK_IOB AND NOT IOBERR AND iobm/ETACK)
|
||
OR (NOT nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND CLK_IOB AND NOT IOBERR AND iobm/DTACKrf AND iobm/DTACKrr)
|
||
OR (NOT nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND CLK_IOB AND NOT IOBERR AND iobm/BERRrf AND iobm/BERRrr)
|
||
OR (NOT nBERR_IOB AND NOT iobm/IOS_FSM_FFd4 AND
|
||
iobm/IOS_FSM_FFd3 AND CLK_IOB AND NOT IOBERR AND iobm/RESrf AND iobm/RESrr));
|
||
|
||
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,CLK_FSB,'0','0',IOL0_CE);
|
||
IOL0_D <= ((NOT nLDS_FSB AND nADoutLE1)
|
||
OR (iobs/IOL1 AND NOT nADoutLE1));
|
||
IOL0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||
|
||
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,CLK_FSB,'0','0');
|
||
IOREQ_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
|
||
NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1)
|
||
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr)
|
||
OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/PS_FSM_FFd2 AND
|
||
nADoutLE1)
|
||
OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT fsb/ASrf AND
|
||
nADoutLE1));
|
||
|
||
FTCPE_IORW0: FTCPE port map (IORW0,IORW0_T,CLK_FSB,'0','0');
|
||
IORW0_T <= ((nROMCS_OBUF.EXP)
|
||
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
|
||
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
|
||
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
|
||
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
|
||
NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
||
cs/nOverlay1 AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
|
||
IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
|
||
IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
|
||
NOT IORW0 AND nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
|
||
NOT IORW0 AND nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
fsb/ASrf AND nADoutLE1)
|
||
OR (IORW0 AND NOT iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||
OR (NOT IORW0 AND iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
|
||
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
|
||
|
||
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,CLK_FSB,'0','0',IOU0_CE);
|
||
IOU0_D <= ((NOT nUDS_FSB AND nADoutLE1)
|
||
OR (iobs/IOU1 AND NOT nADoutLE1));
|
||
IOU0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
|
||
|
||
|
||
RA(0) <= ((A_FSB(10) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(1)));
|
||
|
||
|
||
RA(1) <= ((ram/RASEL AND A_FSB(2))
|
||
OR (A_FSB(11) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(2) <= ((ram/RASEL AND A_FSB(3))
|
||
OR (A_FSB(12) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(3) <= ((A_FSB(13) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(4)));
|
||
|
||
|
||
RA(4) <= ((A_FSB(14) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(5)));
|
||
|
||
|
||
RA(5) <= ((A_FSB(15) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(6)));
|
||
|
||
|
||
RA(6) <= ((A_FSB(16) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(7)));
|
||
|
||
|
||
RA(7) <= ((A_FSB(8) AND ram/RASEL)
|
||
OR (A_FSB(17) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(8) <= ((A_FSB(9) AND ram/RASEL)
|
||
OR (A_FSB(18) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(9) <= ((A_FSB(20) AND ram/RASEL)
|
||
OR (A_FSB(19) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(10) <= A_FSB(21);
|
||
|
||
|
||
RA(11) <= A_FSB(19);
|
||
|
||
FDCPE_RefAck: FDCPE port map (RefAck,RefAck_D,CLK_FSB,'0','0');
|
||
RefAck_D <= (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
|
||
|
||
FTCPE_TimeoutA: FTCPE port map (TimeoutA,TimeoutA_T,CLK_FSB,'0','0');
|
||
TimeoutA_T <= ((TimeoutA AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT TimeoutA AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
|
||
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4))
|
||
OR (NOT TimeoutA AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
|
||
NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
|
||
NOT cnt/RefCnt(4) AND fsb/ASrf));
|
||
|
||
FTCPE_TimeoutB: FTCPE port map (TimeoutB,TimeoutB_T,CLK_FSB,'0','0');
|
||
TimeoutB_T <= ((TimeoutB AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT nAS_FSB AND
|
||
NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND
|
||
NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
|
||
OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND
|
||
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
|
||
|
||
FTCPE_cnt/RefCnt0: FTCPE port map (cnt/RefCnt(0),'1',CLK_FSB,'0','0');
|
||
|
||
FTCPE_cnt/RefCnt1: FTCPE port map (cnt/RefCnt(1),cnt/RefCnt(0),CLK_FSB,'0','0');
|
||
|
||
FTCPE_cnt/RefCnt2: FTCPE port map (cnt/RefCnt(2),cnt/RefCnt_T(2),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(2) <= (cnt/RefCnt(0) AND cnt/RefCnt(1));
|
||
|
||
FTCPE_cnt/RefCnt3: FTCPE port map (cnt/RefCnt(3),cnt/RefCnt_T(3),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(3) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2));
|
||
|
||
FTCPE_cnt/RefCnt4: FTCPE port map (cnt/RefCnt(4),cnt/RefCnt_T(4),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(4) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
|
||
cnt/RefCnt(3));
|
||
|
||
FTCPE_cnt/RefCnt5: FTCPE port map (cnt/RefCnt(5),cnt/RefCnt_T(5),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(5) <= (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
|
||
cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||
|
||
FTCPE_cnt/RefCnt6: FTCPE port map (cnt/RefCnt(6),cnt/RefCnt_T(6),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(6) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(1) AND
|
||
cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||
|
||
FTCPE_cnt/RefCnt7: FTCPE port map (cnt/RefCnt(7),cnt/RefCnt_T(7),CLK_FSB,'0','0');
|
||
cnt/RefCnt_T(7) <= (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
|
||
cnt/RefCnt(1) AND cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
|
||
|
||
FDCPE_cnt/RefDone: FDCPE port map (cnt/RefDone,cnt/RefDone_D,CLK_FSB,'0','0');
|
||
cnt/RefDone_D <= ((NOT cnt/RefDone AND NOT RefAck)
|
||
OR (NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND
|
||
NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND
|
||
NOT cnt/RefCnt(7)));
|
||
|
||
FTCPE_cnt/TimeoutBPre: FTCPE port map (cnt/TimeoutBPre,cnt/TimeoutBPre_T,CLK_FSB,'0','0');
|
||
cnt/TimeoutBPre_T <= ((cnt/TimeoutBPre AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT cnt/TimeoutBPre AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
|
||
NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
|
||
NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
|
||
OR (NOT cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
|
||
NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
|
||
NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
|
||
|
||
FTCPE_cs/nOverlay0: FTCPE port map (cs/nOverlay0,cs/nOverlay0_T,CLK_FSB,NOT nRES,'0');
|
||
cs/nOverlay0_T <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
||
NOT cs/nOverlay0 AND NOT nAS_FSB)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
||
NOT cs/nOverlay0 AND fsb/ASrf));
|
||
|
||
FDCPE_cs/nOverlay1: FDCPE port map (cs/nOverlay1,cs/nOverlay0,CLK_FSB,'0','0',cs/nOverlay1_CE);
|
||
cs/nOverlay1_CE <= (nAS_FSB AND NOT fsb/ASrf);
|
||
|
||
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT CLK_FSB,'0','0');
|
||
|
||
FDCPE_fsb/BERR0r: FDCPE port map (fsb/BERR0r,fsb/BERR0r_D,CLK_FSB,'0','0');
|
||
fsb/BERR0r_D <= ((NOT TimeoutB AND NOT fsb/BERR0r)
|
||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND
|
||
NOT fsb/BERR0r));
|
||
|
||
FDCPE_fsb/BERR1r: FDCPE port map (fsb/BERR1r,fsb/BERR1r_D,CLK_FSB,'0','0');
|
||
fsb/BERR1r_D <= ((NOT BERR_IOBS AND NOT fsb/BERR1r)
|
||
OR (nAS_FSB AND NOT fsb/ASrf));
|
||
|
||
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,CLK_FSB,'0','0');
|
||
fsb/Ready0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||
NOT fsb/Ready0r AND NOT ram/RAMReady)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady));
|
||
|
||
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,CLK_FSB,'0','0');
|
||
fsb/Ready1r_D <= ((A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
||
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
|
||
NOT nADoutLE1)
|
||
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
||
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
|
||
NOT nADoutLE1)
|
||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
|
||
NOT iobs/IOReady)
|
||
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady)
|
||
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND NOT iobs/IOReady));
|
||
|
||
FDCPE_fsb/Ready2r: FDCPE port map (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,'0','0');
|
||
fsb/Ready2r_D <= ((EXP18_.EXP)
|
||
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
|
||
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
|
||
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
|
||
OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
|
||
A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
|
||
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
|
||
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
|
||
OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
|
||
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
|
||
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
|
||
OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
|
||
NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
|
||
A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
|
||
A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r));
|
||
|
||
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,CLK_FSB,'0','0');
|
||
fsb/VPA_D <= ((EXP21_.EXP)
|
||
OR (NOT A_FSB(22) AND TimeoutB AND fsb/VPA AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(21) AND TimeoutB AND fsb/VPA AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
|
||
NOT iobs/IOReady AND NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
|
||
NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
|
||
fsb/VPA AND NOT iobs/IOReady AND NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (EXP12_.EXP)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
NOT cs/nOverlay1 AND NOT fsb/Ready0r AND fsb/VPA AND NOT ram/RAMReady AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
|
||
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
|
||
NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
||
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
|
||
NOT nADoutLE1 AND NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
||
cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND
|
||
NOT nADoutLE1 AND NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (BERR_IOBS AND fsb/VPA AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (fsb/BERR0r AND fsb/VPA AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (fsb/BERR1r AND fsb/VPA AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (A_FSB(23) AND TimeoutB AND fsb/VPA AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439)
|
||
OR (NOT A_FSB(20) AND TimeoutB AND fsb/VPA AND
|
||
NOT $OpTx$$OpTx$FX_DC$355_INV$439));
|
||
|
||
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,CLK2X_IOB,'0','0');
|
||
|
||
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),CLK2X_IOB,'0','0');
|
||
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
|
||
|
||
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),CLK2X_IOB,'0','0');
|
||
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
||
OR (NOT iobm/Er AND iobm/Er2));
|
||
|
||
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),CLK2X_IOB,'0','0');
|
||
iobm/ES_D(2) <= ((NOT iobm/ES(0) AND NOT iobm/ES(2))
|
||
OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
|
||
OR (NOT iobm/Er AND iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
|
||
OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
|
||
|
||
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),CLK2X_IOB,'0','0');
|
||
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
|
||
|
||
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),CLK2X_IOB,'0','0');
|
||
iobm/ES_T(4) <= ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||
iobm/ES(3) AND iobm/Er)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
||
iobm/ES(3) AND NOT iobm/Er2)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND iobm/ES(4)));
|
||
|
||
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,CLK2X_IOB,'0','0');
|
||
iobm/ETACK_D <= (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND iobm/ES(4));
|
||
|
||
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E_IOB,NOT CLK_IOB,'0','0');
|
||
|
||
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd1_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd1_D <= ((iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd2 AND
|
||
NOT iobm/IOS_FSM_FFd1)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd2));
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd2_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
iobm/IOS_FSM_FFd1)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND
|
||
NOT iobm/IOS_FSM_FFd1));
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd3_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/ETACK)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/DTACKrf AND
|
||
iobm/DTACKrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/BERRrf AND
|
||
iobm/BERRrr)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/RESrf AND
|
||
iobm/RESrr));
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd4_D,CLK2X_IOB,'0','0');
|
||
iobm/IOS_FSM_FFd4_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
iobm/IOS_FSM_FFd1)
|
||
OR (iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2 AND
|
||
iobm/IOS_FSM_FFd1)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd2 AND CLK_IOB)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd2 AND NOT iobm/IOREQr));
|
||
|
||
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,CLK2X_IOB,'0','0');
|
||
|
||
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,CLK_FSB,'0','0');
|
||
iobs/Clear1_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1);
|
||
|
||
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,CLK_FSB,'0','0');
|
||
|
||
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,CLK_FSB,'0','0',iobs/Load1);
|
||
|
||
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,CLK_FSB,'0','0');
|
||
iobs/IORW1_T <= ((iobs/Once)
|
||
OR (NOT nADoutLE1)
|
||
OR (nOE_OBUF.EXP)
|
||
OR (NOT nWE_FSB AND NOT iobs/IORW1)
|
||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(20))
|
||
OR (nWE_FSB AND iobs/IORW1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/IORW1));
|
||
|
||
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,CLK_FSB,'0','0');
|
||
iobs/IOReady_T <= ((iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf)
|
||
OR (iobs/Once AND iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
|
||
OR (iobs/Once AND NOT iobs/IOReady AND NOT nAS_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
|
||
OR (iobs/Once AND NOT iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/IOACTr AND NOT IOBERR AND fsb/ASrf AND nADoutLE1));
|
||
|
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FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,CLK_FSB,'0','0',iobs/Load1);
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||
|
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FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,CLK_FSB,'0','0');
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||
iobs/Load1_D <= ((iobs/Once)
|
||
OR (NOT nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
|
||
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21))
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(20))
|
||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
|
||
|
||
FDCPE_iobs/Once: FDCPE port map (iobs/Once,iobs/Once_D,CLK_FSB,'0','0');
|
||
iobs/Once_D <= ((fsb/Ready2r.EXP)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd1)
|
||
OR (NOT iobs/Once AND iobs/PS_FSM_FFd2 AND NOT nADoutLE1)
|
||
OR (NOT iobs/Once AND iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
|
||
NOT iobs/Once)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND NOT iobs/Once)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND NOT iobs/Once)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND NOT iobs/Once)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/Once AND nWE_FSB)
|
||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||
OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/Once)
|
||
OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
|
||
OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd1));
|
||
|
||
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,CLK_FSB,'0','0');
|
||
iobs/PS_FSM_FFd1_D <= ((iobs/PS_FSM_FFd2)
|
||
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
|
||
|
||
FDCPE_iobs/PS_FSM_FFd2: FDCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_D,CLK_FSB,'0','0');
|
||
iobs/PS_FSM_FFd2_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
|
||
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
|
||
cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
|
||
iobs/IOACTr)
|
||
OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
|
||
NOT iobs/IOACTr)
|
||
OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/PS_FSM_FFd2 AND
|
||
NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
|
||
OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
|
||
NOT fsb/ASrf AND nADoutLE1));
|
||
|
||
|
||
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
||
|
||
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,CLK_FSB,'0','0');
|
||
nADoutLE1_D <= ((iobs/Load1)
|
||
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
|
||
|
||
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB,nAS_IOB_D,NOT CLK2X_IOB,'0','0');
|
||
nAS_IOB_D <= ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd2)
|
||
OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd3 AND
|
||
iobm/IOS_FSM_FFd1));
|
||
|