mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-29 12:49:33 +00:00
22 lines
1.4 KiB
XML
22 lines
1.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">"../WarpSE.v" line 139 </arg>Connection to input port '<arg fmt="%s" index="2">Ready2</arg>' does not match port size
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">SW</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">nBG_IOB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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</msg>
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<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">SndRAMCSWR</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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</msg>
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</messages>
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