Warp-SE/cpld/XC95144XL/WarpSE_html/fit/failtable.htm
2022-03-29 04:23:54 -04:00

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<h3 align="center">Failure Table</h3>
<table width="90%" border="1" cellpadding="0" cellspacing="0">
<tr class="pgHeader">
<th align="left">Signal Name</th>
<th align="left">FB1</th>
<th align="left">FB2</th>
<th align="left">FB3</th>
<th align="left">FB4</th>
</tr>
<tr class="pgHeader">
<th align="left">Signal Name</th>
<th align="left">FB5</th>
<th align="left">FB6</th>
<th align="left">FB7</th>
<th align="left">FB8</th>
</tr>
</table>
<table width="90%" border="1" cellpadding="0" cellspacing="0"><table width="90%" border="1" cellpadding="0" cellspacing="0">
<tr><td>Legend:</td></tr>
<tr><td> ce - signal clock enable cannot be placed</td></tr>
<tr><td> clk - signal clock cannot be placed</td></tr>
<tr><td> fbi - insufficient function block inputs available to place signal</td></tr>
<tr><td> io - insufficient I/O pins available to place output</td></tr>
<tr><td> loc - signal cannot be placed in this FB because it is assigned to a different FB</td></tr>
<tr><td> mc - insufficient macrocells available to place signal</td></tr>
<tr><td> oe - signal output enable cannot be placed</td></tr>
<tr><td> pt - insufficient product terms available to place signal</td></tr>
<tr><td> sr - signal set/reset cannot be placed</td></tr>
<tr><td> unk - unknown reason for failure - Please contact Xilinx Support</td></tr>
</table></table>
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