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31 lines
577 B
Verilog
31 lines
577 B
Verilog
module SET(
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input CLK,
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input BACT,
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input [11:1] A,
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input SetCSWR,
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output reg SlowIACK,
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output reg SlowVIA,
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output reg SlowIWM,
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output reg SlowSCC,
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output reg SlowSCSI,
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output reg SlowSnd,
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output reg SlowClockGate,
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output reg [3:0] SlowTimeout);
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reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
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always @(posedge CLK) begin
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if (SetWRr) begin
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SlowTimeout[3:0] <= A[11:8];
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SlowIACK <= A[7];
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SlowVIA <= A[6];
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SlowIWM <= A[5];
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SlowSCC <= A[4];
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SlowSCSI <= A[3];
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SlowSnd <= A[2];
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SlowClockGate <= A[1];
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end
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end
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endmodule
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