mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-29 12:49:33 +00:00
518 lines
20 KiB
Plaintext
518 lines
20 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.91 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.91 secs
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--> Reading design: WarpSE.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "WarpSE.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "WarpSE"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : WarpSE
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../RAM.v" in library work
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Compiling verilog file "../IOBS.v" in library work
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Module <RAM> compiled
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Compiling verilog file "../IOBM.v" in library work
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Module <IOBS> compiled
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Compiling verilog file "../FSB.v" in library work
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Module <IOBM> compiled
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Compiling verilog file "../CS.v" in library work
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Module <FSB> compiled
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Compiling verilog file "../CNT.v" in library work
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Module <CS> compiled
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Compiling verilog file "../WarpSE.v" in library work
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Module <CNT> compiled
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Module <WarpSE> compiled
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No errors in compilation
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Analysis of file <"WarpSE.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <WarpSE> in library <work>.
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Analyzing hierarchy for module <CS> in library <work>.
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Analyzing hierarchy for module <RAM> in library <work>.
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Analyzing hierarchy for module <IOBS> in library <work>.
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Analyzing hierarchy for module <IOBM> in library <work>.
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Analyzing hierarchy for module <CNT> in library <work>.
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Analyzing hierarchy for module <FSB> in library <work>.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <WarpSE>.
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Module <WarpSE> is correct for synthesis.
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Analyzing module <CS> in library <work>.
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Module <CS> is correct for synthesis.
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Analyzing module <RAM> in library <work>.
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Module <RAM> is correct for synthesis.
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Analyzing module <IOBS> in library <work>.
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Module <IOBS> is correct for synthesis.
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Analyzing module <IOBM> in library <work>.
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Module <IOBM> is correct for synthesis.
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Analyzing module <CNT> in library <work>.
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Module <CNT> is correct for synthesis.
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Analyzing module <FSB> in library <work>.
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Module <FSB> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <CS>.
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Related source file is "../CS.v".
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Found 1-bit register for signal <nOverlay>.
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Unit <CS> synthesized.
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Synthesizing Unit <RAM>.
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Related source file is "../RAM.v".
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Found finite state machine <FSM_0> for signal <RS>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 14 |
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| Inputs | 6 |
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| Outputs | 8 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <nCAS>.
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Found 1-bit register for signal <nOE>.
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Found 1-bit register for signal <RAMReady>.
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Found 1-bit register for signal <DTACKr>.
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Found 1-bit register for signal <RASEL>.
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Found 1-bit register for signal <RASEN>.
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Found 1-bit register for signal <RASrf>.
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Found 1-bit register for signal <RASrr>.
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Found 1-bit register for signal <RefDone>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 8 D-type flip-flop(s).
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Unit <RAM> synthesized.
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Synthesizing Unit <IOBS>.
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Related source file is "../IOBS.v".
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Found finite state machine <FSM_1> for signal <TS>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 10 |
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| Inputs | 5 |
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| Outputs | 5 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <IORDREQ>.
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Found 1-bit register for signal <IOL0>.
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Found 1-bit register for signal <IOWRREQ>.
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Found 1-bit register for signal <IONPReady>.
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Found 1-bit register for signal <IOU0>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <ALE1>.
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Found 1-bit register for signal <nBERR_FSB>.
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Found 1-bit register for signal <Clear1>.
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Found 1-bit register for signal <IOACTr>.
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Found 1-bit register for signal <IODONEr>.
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Found 1-bit register for signal <IOL1>.
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Found 1-bit register for signal <IORW1>.
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Found 1-bit register for signal <IOU1>.
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Found 1-bit register for signal <Load1>.
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Found 1-bit register for signal <Sent>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 10 D-type flip-flop(s).
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Unit <IOBS> synthesized.
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Synthesizing Unit <IOBM>.
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Related source file is "../IOBM.v".
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Found finite state machine <FSM_2> for signal <IOS>.
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-----------------------------------------------------------------------
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| States | 7 |
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| Transitions | 13 |
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| Inputs | 5 |
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| Outputs | 7 |
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| Clock | C16M (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <IOBERR>.
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Found 1-bit register for signal <nASout>.
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Found 1-bit register for signal <IOACT>.
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Found 1-bit register for signal <IODONE>.
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Found 1-bit register for signal <nLDS>.
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Found 1-bit register for signal <nUDS>.
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Found 1-bit register for signal <nDinLE>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <nVMA>.
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Found 1-bit register for signal <C8Mr>.
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Found 1-bit register for signal <DoutOE>.
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Found 1-bit register for signal <Er>.
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Found 4-bit up counter for signal <ES>.
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Found 1-bit register for signal <IORDREQr>.
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Found 1-bit register for signal <IOS0>.
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Found 1-bit register for signal <IOWRREQr>.
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Found 1-bit register for signal <VPAr>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 15 D-type flip-flop(s).
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Unit <IOBM> synthesized.
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Synthesizing Unit <CNT>.
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Related source file is "../CNT.v".
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WARNING:Xst:647 - Input <C8M> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <RAMCS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found finite state machine <FSM_3> for signal <IS>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 8 |
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| Inputs | 2 |
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| Outputs | 4 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <RefUrg>.
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Found 1-bit register for signal <RefReq>.
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Found 1-bit register for signal <nBR_IOB>.
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Found 1-bit register for signal <nRESout>.
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Found 1-bit register for signal <AoutOE>.
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Found 1-bit register for signal <QoSReady>.
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Found 2-bit register for signal <Er>.
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Found 12-bit up counter for signal <LTimer>.
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Found 1-bit register for signal <LTimerTC>.
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Found 1-bit register for signal <nIPL2r>.
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Found 2-bit up counter for signal <QS>.
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Found 4-bit up counter for signal <Timer>.
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Found 1-bit register for signal <TimerTC>.
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Found 5-bit up counter for signal <Wait>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 4 Counter(s).
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inferred 9 D-type flip-flop(s).
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Unit <CNT> synthesized.
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Synthesizing Unit <FSB>.
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Related source file is "../FSB.v".
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Found 1-bit register for signal <nVPA>.
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Found 1-bit register for signal <BACTr>.
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Found 1-bit register for signal <nDTACK>.
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Found 1-bit register for signal <ASrf>.
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Summary:
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inferred 4 D-type flip-flop(s).
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Unit <FSB> synthesized.
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Synthesizing Unit <WarpSE>.
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Related source file is "../WarpSE.v".
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WARNING:Xst:647 - Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 1-bit tristate buffer for signal <nAS_IOB>.
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Found 1-bit tristate buffer for signal <nLDS_IOB>.
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Found 1-bit tristate buffer for signal <nRES>.
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Found 1-bit tristate buffer for signal <nUDS_IOB>.
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Found 1-bit tristate buffer for signal <nVMA_IOB>.
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Summary:
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inferred 5 Tristate(s).
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Unit <WarpSE> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Counters : 5
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12-bit up counter : 1
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2-bit up counter : 1
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4-bit up counter : 2
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5-bit up counter : 1
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# Registers : 56
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1-bit register : 55
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2-bit register : 1
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# Tristates : 5
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1-bit tristate buffer : 5
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_3> for best encoding.
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Optimizing FSM <cnt/IS/FSM> on signal <IS[1:2]> with johnson encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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01 | 01
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10 | 11
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11 | 10
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-------------------
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Analyzing FSM <FSM_2> for best encoding.
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Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:7]> with one-hot encoding.
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-------------------
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State | Encoding
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-------------------
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000 | 0000001
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010 | 0000010
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011 | 0000100
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100 | 0001000
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101 | 0010000
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110 | 0100000
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111 | 1000000
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-------------------
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Analyzing FSM <FSM_1> for best encoding.
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Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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11 | 01
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10 | 11
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01 | 10
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-------------------
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <ram/RS/FSM> on signal <RS[1:8]> with one-hot encoding.
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-------------------
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State | Encoding
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-------------------
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000 | 00000001
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100 | 00000010
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001 | 00000100
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010 | 00001000
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011 | 00010000
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101 | 00100000
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110 | 01000000
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111 | 10000000
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-------------------
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 4
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# Counters : 5
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12-bit up counter : 1
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2-bit up counter : 1
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4-bit up counter : 2
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5-bit up counter : 1
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# Registers : 46
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Flip-Flops : 46
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <WarpSE> ...
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Optimizing unit <CS> ...
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implementation constraint: INIT=r : nOverlay
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Optimizing unit <RAM> ...
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implementation constraint: INIT=s : RS_FSM_FFd8
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implementation constraint: INIT=r : RASEL
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implementation constraint: INIT=r : RASrr
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implementation constraint: INIT=r : RASEN
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implementation constraint: INIT=r : RS_FSM_FFd1
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implementation constraint: INIT=r : RS_FSM_FFd2
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implementation constraint: INIT=r : RS_FSM_FFd3
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implementation constraint: INIT=r : RS_FSM_FFd4
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implementation constraint: INIT=r : RS_FSM_FFd5
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implementation constraint: INIT=r : RS_FSM_FFd6
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implementation constraint: INIT=r : RS_FSM_FFd7
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implementation constraint: INIT=r : RASrf
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Optimizing unit <IOBS> ...
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implementation constraint: INIT=r : IOACTr
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implementation constraint: INIT=r : TS_FSM_FFd2
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implementation constraint: INIT=r : Sent
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implementation constraint: INIT=r : TS_FSM_FFd1
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Optimizing unit <FSB> ...
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implementation constraint: INIT=r : ASrf
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Optimizing unit <IOBM> ...
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implementation constraint: INIT=s : IOS_FSM_FFd7
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implementation constraint: INIT=r : DoutOE
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implementation constraint: INIT=r : IOS_FSM_FFd6
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implementation constraint: INIT=r : IOS_FSM_FFd1
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implementation constraint: INIT=r : IOS_FSM_FFd2
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implementation constraint: INIT=r : IOS_FSM_FFd3
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implementation constraint: INIT=r : IOS_FSM_FFd4
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implementation constraint: INIT=r : IOS_FSM_FFd5
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Optimizing unit <CNT> ...
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implementation constraint: INIT=r : IS_FSM_FFd2
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implementation constraint: INIT=r : Wait_4
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implementation constraint: INIT=r : Wait_0
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implementation constraint: INIT=r : Wait_1
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implementation constraint: INIT=r : Wait_2
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implementation constraint: INIT=r : Wait_3
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implementation constraint: INIT=r : Timer_3
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implementation constraint: INIT=r : Timer_0
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implementation constraint: INIT=r : Timer_1
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implementation constraint: INIT=r : IS_FSM_FFd1
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implementation constraint: INIT=r : Timer_2
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : WarpSE.ngr
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Top Level Output File Name : WarpSE
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : Yes
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Target Technology : XC9500XL CPLDs
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Macro Preserve : YES
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XOR Preserve : YES
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Clock Enable : YES
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wysiwyg : NO
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Design Statistics
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# IOs : 79
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Cell Usage :
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# BELS : 634
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# AND2 : 201
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# AND3 : 27
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# AND4 : 9
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# AND5 : 4
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# AND7 : 1
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# AND8 : 3
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# GND : 6
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# INV : 238
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# OR2 : 104
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# OR3 : 14
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# OR4 : 4
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# VCC : 1
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# XOR2 : 22
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# FlipFlops/Latches : 103
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# FD : 67
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# FDC : 2
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# FDCE : 33
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# FDP : 1
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# IO Buffers : 78
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# IBUF : 35
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# IOBUFE : 1
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# OBUF : 38
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# OBUFE : 4
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=========================================================================
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Total REAL time to Xst completion: 50.00 secs
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Total CPU time to Xst completion: 49.19 secs
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-->
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Total memory usage is 294896 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 3 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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