112 lines
3.3 KiB
Verilog
112 lines
3.3 KiB
Verilog
module CNT(
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/* C16M clock */
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input C16M,
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/* FSB clock and bus active signal */
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input FCLK, input BACT,
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/* Refresh request */
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output reg RefReq, output RefUrgent,
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/* BERR and QoS speed limit output */
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output reg BERRTimeout, output reg QoSGate,
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/* Reset, switch, button */
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input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
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/* Configuration outputs */
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output reg nBR_IOB, output reg FastROMEN, output reg C20MEN, output reg C25MEN);
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/* Timer counts from 0 to 11100000 (224) -- 225 states == 14.36 uS */
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reg [7:0] Timer = 0;
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wire TimerTC = Timer[7:5]==3'b111;
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always @(posedge C16M) Timer <= TimerTC ? 0 : Timer+1;
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/* Refresh timer outputs
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* ___ _______________________________________
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* RefReq |___________| |_________
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* ___^ Timer==0 ^ Timer==17 _____________^ Timer==0
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* RefUrg |_____________________________________| |_________
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* ^ Timer==0 ^ Timer==128 ^ Timer==0
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*/
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assign RefUrgent = Timer[7];
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always @(posedge C16M) begin
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if (Timer[4]) RefREQ <= 1;
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else if (TimerTC) RefREQ <= 0;
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end
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/* NBACT - "Narrow BACT" in FCLK clock domain */
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reg [1:0] BACTCnt = 0;
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reg NBACT;
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always @(posedge FCLK) begin
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if (!BACT) begin
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BACTCnt <= 0;
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NBACT <= 0;
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end else begin
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BACTCnt <= BACTCnt+1;
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if (BACTCnt==2'b11 && BACT) NBACT <= 1;
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end
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end
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/* NBACTr - NBACT synchronized to C16M clock domain */
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reg NBACTr;
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always @(posedge C16M) NBACTr <= NBACT;
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/* BERR generation in C16M clock domain */
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reg BERRArm = 0;
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reg BERRTimeout = 0;
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always @(posedge C16M) begin
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if (NBACTr && TimerTC) begin
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if (BERRArm) BERRTimeout <= 1;
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end else if (!NBACTr) begin
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BERRArm <= 0;
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BERRTimeout <= 0;
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end
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end
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/* Sound QoS */
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always @(posedge C16M) begin
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QoSGate <= Timer[7:6]==2'b11;
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end
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/* Button/switch synchronization */
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reg RESr, IPL2r;
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wire DisableSw = SW[1];
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reg DisableBtn;
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wire FastROMSw = !SW[2];
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reg FastROMBtn;
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always @(posedge C16M) begin
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DisableBtn <= !nRES;
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FastROMBtn <= !nIPL2;
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end
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/* Startup sequence control */
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reg PORDone = 0;
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reg [3:0] SC; // Startup counter
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always @(posedge C16M) if (PORDone && TimerTC) SC <= SC+1; // SC increment
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always @(posedge C16M) begin
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if (!PORDone) begin
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if (!nRESr) begin // While Mac is asserting POR...
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nRESout <= 1; // Disable reset
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nBR_IOB <= 1; // Disable bus request
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end else begin // Once Mac disbles POR...
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nRESout <= 0; // Re-enable reset
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PORDone <= 1; // Mark POR done
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// Decode buttons
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if ((DisableSw ^ DisableBtn) && !FastROMBtn) begin
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// Disable switch XOR disable button and no ROM button
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nBR_IOB <= 1; // Don't request Mac bus
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FastROMEN <= 0; // Fast ROM enable is don't care
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end else if (( (DisableSw ^ DisableBtn) && FastROMBtn) ||
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(!(DisableSw ^ DisableBtn))) begin
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// Disable switch XOR disable button and ROM button
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// Or neither pressed/enabled
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// Or both pressed/enabled
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nBR_IOB <= 0; // Request Mac bus
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FastROMEN <= FastROMSw ^ FastROMBtn;
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end
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end
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end else if (SC[3:2]==2'b11) nRESout <= 1; // Release reset to run after 12 refresh cycles
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end
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// Enable both oscillators... only mount one
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assign C20MEN = 1;
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assign C25MEN = 1;
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endmodule
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