mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-28 20:52:22 +00:00
148 lines
3.4 KiB
Verilog
148 lines
3.4 KiB
Verilog
module WarpSE(
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input [23:1] A_FSB,
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input nAS_FSB,
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input nLDS_FSB,
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input nUDS_FSB,
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input nWE_FSB,
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output nDTACK_FSB,
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output nVPA_FSB,
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output nBERR_FSB,
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input CLK_FSB,
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input CLK2X_IOB,
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input CLK_IOB,
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input E_IOB,
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input nDTACK_IOB,
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input nVPA_IOB,
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output nVMA_IOB,
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output nAS_IOB,
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output nUDS_IOB,
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output nLDS_IOB,
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output nBR_IOB,
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input nBG_IOB,
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input nBERR_IOB,
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inout nRES,
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input nIPL2,
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output nROMCS,
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output nRAMLWE,
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output nRAMUWE,
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output nROMWE,
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output nRAS,
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output nCAS,
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output [11:0] RA,
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output nOE,
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output nADoutLE0,
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output nADoutLE1,
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output nAoutOE,
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output nDoutOE,
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output nDinOE,
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output nDinLE,
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input [3:1] SW,
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output C20MEN,
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output C25MEN);
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/* Reset input and open-drain output */
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wire nRESin = nRES;
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wire nRESout;
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assign nRES = !nRESout ? 1'b0 : 1'bZ;
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/* AS cycle detection */
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wire BACT;
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/* Refresh request/ack signals */
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wire RefReq, RefUrgent;
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/* Fast ROM enable setting */
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wire FastROMEN;
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wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR;
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CS cs(
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/* Setting input */
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FastROMEN,
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/* MC68HC000 interface */
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A_FSB[23:08], CLK_FSB, nRESin, nWE_FSB,
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/* AS cycle detection */
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BACT,
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/* Device select outputs */
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IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR);
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wire Ready_RAM;
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RAM ram(
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/* MC68HC000 interface */
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CLK_FSB, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
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/* AS cycle detection */
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BACT,
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/* Select and ready signals */
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RAMCS, ROMCS, Ready_RAM,
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/* Refresh Counter Interface */
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RefReq, RefUrgent,
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/* DRAM and NOR flash interface */
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RA[11:0], nRAS, nCAS,
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nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
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wire Ready_IOBS, BERR_IOBS;
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wire IOREQ, IOACT, IOBERR;
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wire ALE0S, ALE0M, ALE1;
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assign nADoutLE0 = ~(ALE0S || ALE0M);
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assign nADoutLE1 = ~ALE1;
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wire IORW0, IOL0, IOU0;
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IOBS iobs(
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/* MC68HC000 interface */
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CLK_FSB, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
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/* AS cycle detection, FSB BERR */
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BACT,
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/* Select and ready signals */
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IOCS, IOPWCS, Ready_IOBS, BERR_IOBS,
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/* Read data OE control */
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nDinOE,
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/* IOB Master Controller Interface */
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IOREQ, IOACT, IOBERR,
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/* FIFO primary level control */
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ALE0S, IORW0, IOL0, IOU0,
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/* FIFO secondary level control */
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ALE1);
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wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
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assign nAS_IOB = nAoutOE ? 1'bZ : nAS_IOBout;
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assign nLDS_IOB = nAoutOE ? 1'bZ : nLDS_IOBout;
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assign nUDS_IOB = nAoutOE ? 1'bZ : nUDS_IOBout;
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assign nVMA_IOB = nAoutOE ? 1'bZ : nVMA_IOBout;
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IOBM iobm(
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/* PDS interface */
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CLK2X_IOB, CLK_IOB, E_IOB,
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nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
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nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
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/* PDS address and data latch control */
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nAoutOE, nDoutOE, ALE0M, nDinLE,
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/* IO bus slave port interface */
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IOACT, IOBERR,
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IOREQ, IOL0, IOU0, IORW0);
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wire BERRTimeout, QoSReady;
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CNT cnt(
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/* C16M clock */
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C16M,
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/* FSB clock and bus active signal */
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FCLK, BACT,
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/* Refresh request */
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RefReq, RefUrgent,
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/* BERR and QoS speed limit output */
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BERRTimeout, QoSReady,
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/* Reset, switch, button */
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SW[3:1], nRESin, nRESout, nIPL2,
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/* Configuration outputs */
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nBR_IOB, FastROMEN, C20MEN, C25MEN);
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FSB fsb(
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/* MC68HC000 interface */
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CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB,
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/* AS cycle detection */
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BACT,
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/* Ready and IA inputs */
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Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady),
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/* BERR inputs */
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(~IOCS && BERRTimeout), BERR_IOBS,
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/* Interrupt acknowledge select */
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IACS);
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endmodule
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