mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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151 lines
2.9 KiB
Verilog
151 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:40:18 10/23/2021
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// Design Name: RAM
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// Module Name: C:/Users/zanek/Documents/GitHub/SE-030/cpld/XC95144XL/test.v
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// Project Name: MXSE
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: RAM
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module test;
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// Inputs
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reg CLK;
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reg [21:1] A;
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reg nWE;
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reg nAS;
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reg nLDS;
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reg nUDS;
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reg CACT;
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reg RAMCS;
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reg ROMCS;
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reg RefReq;
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reg RefUrgent;
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// Outputs
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wire Ready;
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wire RefAck;
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wire [11:0] RA;
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wire nRAS;
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wire nCAS;
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wire nLWE;
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wire nUWE;
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wire nOE;
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wire nROMCS;
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wire nROMWE;
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// Instantiate the Unit Under Test (UUT)
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RAM uut (
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.CLK(CLK),
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.A(A),
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.nWE(nWE),
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.nAS(nAS),
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.nLDS(nLDS),
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.nUDS(nUDS),
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.CACT(CACT),
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.RAMCS(RAMCS),
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.ROMCS(ROMCS),
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.Ready(Ready),
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.RefReq(RefReq),
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.RefUrgent(RefUrgent),
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.RefAck(RefAck),
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.RA(RA),
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.nRAS(nRAS),
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.nCAS(nCAS),
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.nLWE(nLWE),
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.nUWE(nUWE),
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.nOE(nOE),
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.nROMCS(nROMCS),
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.nROMWE(nROMWE)
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);
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initial begin
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CLK = 0;
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RAMCS = 0; ROMCS = 0; CACT = 0;
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RefReq = 0; RefUrgent = 0;
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nAS = 1; nLDS = 1; nUDS = 1; nWE = 1;
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A = 0;
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#100;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5;
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A = 8195; #5; ROMCS = 1;
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CLK = 1; #5; #5; #5; #5;
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nAS = 0; nLDS = 0; nUDS = 0; nWE = 1; #5; CACT = 1;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; RefUrgent = 1; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; RefUrgent = 0; #5; #5; #5; #5;
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CLK = 0; #5; CACT = 0; #5; #5; #5;
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nAS = 1; nLDS = 1; nUDS = 1; nWE = 1; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; A = 0; #5; ROMCS = 0;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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CLK = 0; #5; #5; #5; #5; #5;
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CLK = 1; #5; #5; #5; #5; #5;
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end
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endmodule
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