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https://github.com/garrettsworkshop/Warp-SE.git
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38 lines
1.0 KiB
Verilog
38 lines
1.0 KiB
Verilog
module FSB(
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/* MC68HC000 interface */
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input FCLK, input nAS, output reg nDTACK, output reg nVPA,
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/* MC68HC000 clock enable */
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input MCKEi, output reg MCKE,
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/* AS cycle detection */
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output BACT, output reg BACTr,
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/* Ready inputs */
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input ROMCS,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input IOQoSEN,
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/* Interrupt acknowledge select */
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input IACKCS);
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/* MC68k clock enable */
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always @(negedge FCLK) MCKE <= MCKEi;
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/* AS cycle detection */
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reg ASrf = 0;
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always @(negedge FCLK) begin ASrf <= !nAS; end
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assign BACTu = !nAS || ASrf;
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assign BACT = BACTu && MCKE;
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always @(posedge FCLK) BACTr <= BACT;
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/* DTACK/VPA control */
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wire Ready = (RAMCS && !IOQoSEN && RAMReady && !IOPWCS) ||
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(RAMCS && !IOQoSEN && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS && !IOQoSEN) ||
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(IONPReady);
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACKCS);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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else nVPA <= !(Ready && BACT && IACKCS);
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end
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endmodule
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