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11 lines
190 B
Plaintext
11 lines
190 B
Plaintext
// Created using Xilinx Cse Software [ISE - 14.7]
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// Date: Tue Oct 01 01:09:06 2024
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TRST OFF;
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ENDIR IDLE;
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ENDDR IDLE;
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STATE RESET;
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STATE IDLE;
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FREQUENCY 1E6 HZ;
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FREQUENCY 1E6 HZ;
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