79 lines
1.7 KiB
Verilog
79 lines
1.7 KiB
Verilog
module FSB(
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/* MC68HC000 interface */
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input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR,
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/* AS cycle detection */
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output BACT, output LBACT,
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/* Ready inputs */
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input Ready0, input Ready1, input Ready2,
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/* BERR inputs */
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input BERR0, input BERR1,
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/* Interrupt acknowledge select */
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input IACS);
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/* AS cycle detection */
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reg ASrf = 0;
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always @(negedge FCLK) begin ASrf <= ~nAS; end
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assign BACT = ~nAS || ASrf; // BACT - bus active
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/* LBACT - "Long BACT" */
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reg [1:0] BACTCnt = 0;
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reg LBACT;
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always @(posedge FCLK) begin
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if (!BACT) begin
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BACTCnt <= 0;
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LBACT <= 0;
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end else begin
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BACTCnt <= BACTCnt+1;
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if (BACTCnt==2'b11 && BACT) LBACT <= 1;
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end
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end
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/* Ready generation and bypass */
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reg Ready0r, Ready1r, Ready2r;
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wire Ready = (Ready0 || Ready0r) &&
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(Ready1 || Ready1r) &&
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(Ready2 || Ready2r);
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always @(posedge FCLK) begin
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if (~BACT) begin
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Ready0r <= 0;
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Ready1r <= 0;
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Ready2r <= 0;
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end else begin
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if (Ready0) Ready0r <= 1;
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if (Ready1) Ready1r <= 1;
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if (Ready2) Ready2r <= 1;
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end
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end
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/* BERR generation */
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reg BERR0r, BERR1r;
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always @(posedge FCLK) BERR0r <= BERR0;
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always @(posedge FCLK) BERR1r <= BERR1;
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reg BERREN = 0;
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reg BERRCNT = 0;
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always @(posedge FCLK) begin
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if (~BACT) begin
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BERREN <= 0;
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BERRCNT <= 0;
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end else begin
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BERRCNT <= BERRCNT+1;
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BERREN <= BERRCNT==3'b111;
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end
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end
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assign nBERR = ~(~nAS && BERREN && (BERR0r || BERR1r));
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/* DTACK/VPA control */
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reg VPA;
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assign nVPA = ~(~nAS && VPA);
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always @(posedge FCLK) begin
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if (~BACT) begin
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nDTACK <= 1;
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VPA <= 0;
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end else if (Ready && ~BERR) begin
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nDTACK <= IACS;
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VPA <= IACS;
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end
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end
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endmodule
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