#include #include #include #include "ports.h" #define TMS_PORT PORTC #define TMS_PIN 3 #define TCK_PORT PORTC #define TCK_PIN 2 #define TDO_PORT PINC #define TDO_PIN 4 #define TDI_PORT PORTC #define TDI_PIN 5 /* setPort: Implement to set the named JTAG signal (p) to the new value (v).*/ void setPort(short p,short val) { if (p==TMS) { if (val) TMS_PORT |= (1<= 50L ) { /* Make sure TCK is low during wait for XC18V00/XCFxxS */ /* Or, a running TCK implementation as shown above is an OK alternate */ setPort( TCK, 0 ); /* Use Windows Sleep(). Round up to the nearest millisec */ _sleep( ( microsec + 999L ) / 1000L ); } else /* Satisfy FPGA JTAG configuration, startup TCK cycles */ { for ( i = 0; i < microsec; ++i ) { pulseClock(); } } #endif #if 0 /* Alternate implementation */ /* This implementation is valid for only XC9500/XL/XV, CoolRunner/II CPLDs, XC18V00 PROMs, or Platform Flash XCFxxS/XCFxxP PROMs. This implementation does not work with FPGAs JTAG configuration. */ /* Make sure TCK is low during wait for XC18V00/XCFxxS PROMs */ /* Or, a running TCK implementation as shown above is an OK alternate */ setPort( TCK, 0 ); /* Use Windows Sleep(). Round up to the nearest millisec */ _sleep( ( microsec + 999L ) / 1000L ); #endif }