164 lines
2.7 KiB
Verilog
Executable File
164 lines
2.7 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 15:13:07 11/30/2011
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// Design Name: floppyemu
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// Module Name: C:/Users/steve/Documents/floppyemu/CPLD-Xilinx/testbench.v
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// Project Name: floppyemu
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: floppyemu
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module testbench;
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// Inputs
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reg clk;
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reg wr;
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// Outputs
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wire [7:0] wrData;
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wire rdAckWrByte;
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// Instantiate the Unit Under Test (UUT)
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floppyemu uut (
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.clk(clk),
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.wr(wr),
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.wrData(wrData),
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.rdAckWrByte(rdAckWrByte)
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);
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initial begin
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clk = 0;
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end
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always begin
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#70 clk = 1;
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#70 clk = 0;
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end
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initial begin
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// Initialize Inputs
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wr = 0;
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// Wait 100 ns for global reset to finish
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#4000;
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// send 10-bit sync byte
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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#2000 ;
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// send 10-bit sync byte
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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#2000 ;
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// send 10-bit sync byte
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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#2000 ;
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// send 10-bit sync byte
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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#2000 ;
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// send 10-bit sync byte
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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#2000 ;
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// D5 = 1101 0101
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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// AA = 1010 1010
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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#2000 ;
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// 96 = 1001 0110
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#2000 wr = ~wr;
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#2000 ;
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#2000 ;
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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// 96 = 1001 0110
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#2000 wr = ~wr;
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#2000 ;
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#2000 ;
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#2000 wr = ~wr;
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#2000 ;
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#2000 wr = ~wr;
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#2000 wr = ~wr;
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#2000 ;
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$stop;
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end
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endmodule
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