Reorganize, demonstrate overly ambitious project idea.

This commit is contained in:
Andrew Makousky 2020-08-01 16:53:34 -05:00
parent 9808776ec3
commit 32f0676c91
35 changed files with 29693 additions and 0 deletions

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firmware/README.md Normal file
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## Firmware
This directory contains firmware images required for the various ROM
chips in the hardware design.

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# 3d_prints
This directory contains 3D printable parts like the external enclosure
case, etc.

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hardware/fpga/README.md Normal file
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# fpga
This directory contains hardware description language (Verilog/VHDL)
source files for the Field Programmable Gate Arrays (FPGAs) that
implement the functions of the custom Application Specific Integrated
Circuits (ASICs) found in the original hardware.

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hardware/pcb/README.md Normal file
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# pcb
This directory contains Printed Circuit Board (PCB) designs.

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hardware/pcb/mlb/CPU+FPU.sch Normal file

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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(kicad_pcb (version 4) (host kicad "dummy file") )

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update=Monday, May 25, 2020 at 12:53:54 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr USLedger 17000 11000
encoding utf-8
Sheet 1 10
Title "Macintosh SE30 Main Logic Board"
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1050 900 2800 2050
U 5EC6E0CC
F0 "CPU&FPU" 50
F1 "CPU+FPU.sch" 50
$EndSheet
$Sheet
S 4250 900 2800 2050
U 5EC6E148
F0 "ROM & RAM Muxes" 50
F1 "ROM+RAM Muxes.sch" 50
$EndSheet
$Sheet
S 7450 900 2800 2050
U 5EC6E1BF
F0 "GLUE & RAM SIMMs" 50
F1 "GLUE+RAM SIMMs.sch" 50
$EndSheet
$Sheet
S 10700 900 2800 2050
U 5EC6E211
F0 "VIA1, VIA2, RTC & ADB" 50
F1 "VIA1+VIA2+RTC+ADB.sch" 50
$EndSheet
$Sheet
S 1050 3600 2800 2050
U 5EC6E28B
F0 "Video Interface" 50
F1 "Video Interface.sch" 50
$EndSheet
$Sheet
S 4250 3600 2800 2050
U 5EC6E34D
F0 "SWIM & SCSI Interface" 50
F1 "SWIM+SCSI Interface.sch" 50
$EndSheet
$Sheet
S 7450 3600 2800 2050
U 5EC6E3D0
F0 "Serial Interface & Sound Interface" 50
F1 "Serial Interface + Sound Interface.sch" 50
$EndSheet
$Sheet
S 10700 3550 2800 2050
U 5EC6E43E
F0 "Power Connector, Pullups & Pulldowns" 50
F1 "Power Connector + Pullups + Pulldowns.sch" 50
$EndSheet
$Sheet
S 1000 6200 2800 2050
U 5EC6E4FC
F0 "Unknown" 50
F1 "Unknown.sch" 50
$EndSheet
$EndSCHEMATC

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# mlb
This directory contains the schematics and circuit board design for
the Macintosh SE/30 Main Logic Board (MLB).

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr USLedger 17000 11000
encoding utf-8
Sheet 10 10
Title "Unknown"
Date "2020-05-18"
Rev "1"
Comp "Recreation of Apple engineering drawing 050-0253-01"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 5250 5400 0 197 ~ 0
This page is referenced in the other drawings, \nbut its contents are unknown. It was possibly a \n“bed of nails” flying probe schematic.
$EndSCHEMATC

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# Generated Artifacts
This directory contains files/data that have been generated from
source files within.

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(sym_lib_table
(lib (name Macintosh_SE_30_Components)(type Legacy)(uri "${KIPRJMOD}/SE30 Components Library/Macintosh_SE_30_Components.lib")(options "")(descr ""))
)