BBU: Commit work-in-progress, lots of corrections to be made.
This commit is contained in:
Andrew Makousky
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62d2e920e7
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4fa9303844
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@ -50,6 +50,10 @@
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`define RAMSZ_EN_4M 7'b1000000
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`define RAMSZ_ENI_4M 6
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// Please note: If we don't list the configuration in one of the
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// following the tables, it's not supported by the BBU. The BBU is a
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// gate array, not a microcontroller!
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// The main and alternate screen buffer memory addresses are
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// calculated by subtracting a constant from the installed RAM size.
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// Deltas: main -0x5900, alt. -0xd900.
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@ -62,10 +66,6 @@
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// 2.5MB: main 0x27a700, alt 0x272700.
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// 4MB: main 0x3fa700, alt 0x3f2700.
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// Please note: If we don't list the configuration in the table, it's
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// not supported by the BBU. The BBU is a gate array, not a
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// microcontroller!
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// Table of video memory base addresses.
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`define vid_main_addr_128k 24'h1a700
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`define vid_alt_addr_128k 24'h12700
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@ -94,10 +94,6 @@
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// 2.5MB: main 0x27fd00, alt. 0x27a100.
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// 4MB: main 0x3ffd00, alt. 0x3fa100.
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// Please note: If we don't list the configuration in the table,
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// it's not supported by the BBU. The BBU is a gate array, not a
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// microcontroller!
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// Table of sound and disk speed memory base addresses.
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`define snddsk_main_addr_128k 24'h1fd00
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`define snddsk_alt_addr_128k 24'h1a100
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@ -116,11 +112,6 @@
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/* Top-level module for the BBU.
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TODO Abbreviations legend, here since they are not noted elsewhere:
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RDQ = RAM Data Value
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PMCYC = Processor Memory Cycle
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Undocumented signal but assumed to exist:
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64KRAM: Here we assign it to pin 21 for our own experimentation, a
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@ -164,17 +155,7 @@ module bbu_master_ctrl
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// The Macintosh SE deprecated SNDPG2. Nevertheless... for the
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// sake of possibly making quasi-hardware replicas of earlier
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// Macintosh computers easier, we will preserve an implementation
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// here anyways. As for the OVERLAY signal, we'll have to use Mini
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// vMac's guess on how to implement it. At boot, the ROM
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// exclusively accesses the ROM overlay addresses and the remapped
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// RAM address when setting up. When it is done, it jumps into the
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// standard ROM address access. As soon as the BBU detects this
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// memory access (any address in the standard ROM address space),
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// it switches the overlay, and it cannot be switched back except
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// by a RESET signal.
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// So yes... it turns out the BBU must actually do address bus
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// snooping.
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// here anyways.
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// Essential sequential logic RESET and clock signals
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input wire n_res; // *RESET signal
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@ -235,15 +216,22 @@ module bbu_master_ctrl
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// Note tristate inout ... 'bz for high impedance. 8'bz for wide.
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// In order to implement the memory overlay switch, we must snoop
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// the address bus. These are the registers we use to store the
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// address multiplexor outputs.
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// Full DRAM address bus snooping? I almost thought this was
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// required to implement some functions, but it turns out it isn't,
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// partial address bus snooping is good enough. Nevertheless, I'll
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// preserve the implementation as it could be useful for BBU mods.
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reg [7:0] row_snoop; reg [7:0] col_snoop;
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// Installed RAM size.
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wire [23:0] ramsz;
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// SCSI support: Handle chip select, and handle DMA.
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// SCSI support: Handle chip select, and handle DMA. Important!
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// Never have *DACK and *SCSI active simultaneously. Okay, so
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// let's get this straight. When we would normally assert *DTACK,
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// we release *SCSI and wait for SCSI.DRQ. Then when we receive
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// it, we can assert *DTACK and also *DACK, with a timer to
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// deassert *DACK. Important! Make sure we do not go faster than
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// the minimum read/write pulse width of the SCSI chip.
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// Important! How to handle SCSI DMA... according to Guide to the
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// Macintosh family hardware, page 126, this is "pseudo-DMA" mode.
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@ -255,9 +243,13 @@ module bbu_master_ctrl
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// `*DTACK` is tri-stated according to the manual when `*EXTDTK`
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// (`*EXT.DTACK`) is asserted.
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// TODO: How do we know if DMA mode is true? Do we have to snoop
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// the address but to get this information.
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// Now, here's the golden rule: "If any access has not terminated
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// within 265 ms, the BBU asserts the bus error signal /BERR."
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// There you go, that's how it is driven. So, another thing,
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// There you go, that's how it is driven, though the condition only
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// happens for PDS and SCSI accesses. So, another thing,
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// yes... there must be at least a nominal delay to assert `*DTACK`
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// to allow PDS cards to intervene by asserting `*EXTDTK` first.
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@ -407,6 +399,17 @@ module clock_div (n_res, c16m, c8m, c3_7m, c2m_e, n_pmcyc, pmcyc_pt);
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// PLEASE NOTE. Macintosh SE/30 takes one access cycle every
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// 15.6us for DRAM refresh.
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// So, what's the secret sauce of the Macintosh SE being more
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// performant in memory access? Guide to the Macintosh family
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// hardware, page 401. During the BBU memory access cycle time,
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// unlike earlier models that would only read one word, the BBU
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// reads two 16-bit words. Yes, so it does do buffering! This
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// allows the CPU to have free access to the next two cycles. So,
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// the word is hard and strong now, `*PMCYC` is not a simple 1MHz
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// clock, but has a much more complex timing circuit. That equates
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// to a 200% memory access speedup during screen scanning in the
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// Macintosh SE compared to the Macintosh Plus.
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/* Inside Macintosh claims that the serial clock is 3.672 MHz.
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Clock multiplication (via PLL) and division can be used to
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generate this from the 15.6672 MHz clock as follows:
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@ -432,9 +435,9 @@ module clock_div (n_res, c16m, c8m, c3_7m, c2m_e, n_pmcyc, pmcyc_pt);
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And yes, even with that introduced phase/period error, the
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downstream hardware apparently still works just fine, thanks to
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the divide-by-16 in front of the SCC's internal baud rate
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generator. This gives you a max baud of 230 kbits/sec, with a
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phase/period error of 1/(16*16) = 0.39%.
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*/
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generator. This gives you a max baud of 230.4 kbits/sec, with a
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phase/period error of 1/(16*16) = 0.39%. This is the same baud
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as AppleTalk. */
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// TODO EVALUATE: Optimize this to minimize the number of register
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// bits required, while still preserving ideal frequency division
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@ -699,7 +702,24 @@ endmodule
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charge, you can do better! And indeed, that note only appears to
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apply to the Macintosh Plus, not the Macintosh SE, as it is listed
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in that section.
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But, for the sake of Macintosh Plus recreation, please note. The
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TSG PAL places one of the high-frequency phase indicator signals on
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D0 of the address bus, I assume it is the 1 MHz *PMCYC signal. A
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multiple address read instruction is used to read three consecutive
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data values from the address bus in synchronous I/O mode (due to
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using address 0xf00000), so each address read is either 10 or 20
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CPU cycles long. This will sample the phase at a few different
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points. The phase readings are added together, if they are zero or
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one, then we are "in-phase." Otherwise, phase readings 2 and 3 are
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considered "out-of-phase" so we access a word-width address in the
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SCC range to shift the high frequency timing by 128 ns (one CPU
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clock cycle at 8 MHz).
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The important thing to remember is that every MC68000 instruction
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executes for an even number of clock cycles (divisible by 2), and
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there is no pipelining in these early CPUs.
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TODO FIXME: Guide to the Macintosh family hardware, page 127.
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Okay, so this is how to interpret the information about the
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boot-time overlay for the alternate RAM location. Only a 2MB zone
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@ -993,6 +1013,77 @@ module a0_to_ds (a0, n_uds, n_lds);
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assign n_lds = ~a0;
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endmodule
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// TODO: So this is how the fastest CPU access state machine workss.
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// *AS is started to be asserted on the rising edge of the CPU clock
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// at S2, but it is not guaranteed clearly asserted until the falling
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// edge of S2. Between this time, we must assert *DTACK before the
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// falling edge of S4. So yes, we effectively have a maximum of two
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// 16 MHz cycles to react, but better if we can get it done in 1.5
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// cycles at 16 MHz. We must assert *DTACK before 10 ns of the end,
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// so better to go 30 ns before the end, i.e. half of a 16 MHz clock
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// cycle.
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// So, point in hand, we need to design our logic to work very fast
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// within these constraints. First, we have a cycle counter runs on
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// the _falling edge_ of the clock. We only count one. Then, we have
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// a "subcycle counter" which is really just combinatorial logic. We
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// must only use combinatorial logic in order to be able to assert
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// signals sub-cycle in a way that hopefully still works on an FPGA.
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// If this really only works on an ASIC, though, our next best option
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// is to use a 32 MHz PLL to satisfy the timing requirements. Also,
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// it's important to understand, when using combinatorial logic to
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// effectively double the clock frequency, understanding signal
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// propagation delay is critical.
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// Here, we assume the rising edge of C16M is synced to the rising
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// edge of C8M, otherwise this won't work!
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// There's good reason to be concerned about glitching when not using
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// register-buffered outputs on a sequential clock. But, yeah,
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// hardware-wise, this is the simplest way to do clock frequency
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// doubling, and if it works like the 3.686 MHz clock with
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// phase/period error, history be told. F.Y.I. Anecdotal evidence
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// hints that the Macintosh Plus may have used this combinatorial
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// logic hackery on clock signals in its PALs. But it was still
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// driven by clock C16M and was a registered PAL? Maybe I better just
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// look down its datasheet real good, check that it uses typical
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// latching. PAL16R4.
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// Okay, here's the deal. We can get this to work reasonably without
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// glitching through the means of programmable slew rate limiting
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// filter circuits built into the FPGA at the pin terminals. But that
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// is the necessity if we go that path.
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module dram_fast_test (c16m, c8m, n_res, n_as);
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input wire c16m;
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input wire c8m;
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input wire n_res;
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input wire n_as;
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reg state_buf;
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wire state0, state1, state2, state3;
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// wire state4;
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assign state0 = n_as;
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assign state1 = ~n_as & ~state_buf & c16m & ~c8m;
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assign state2 = ~n_as & ~state_buf & ~c16m & ~c8m;
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assign state3 = ~n_as & state_buf & c16m & c8m;
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// assign state4 = ~n_as & state_buf & ~c16m & c8m;
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always @(negedge n_res) begin
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state_buf <= 0;
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end
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always @(posedge c16m) begin
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if (n_res) begin
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if (~n_as)
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state_buf <= 1;
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else
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state_buf <= 0;
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end
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end
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endmodule
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// Stateful advancement DRAM controller logic for CPU memory accesses.
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module dramctl_cpu (n_res, clk, r_n_w, c2m,
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ram_r_n_w, n_as, n_ras, n_cas,
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