From 7d7a495caea4d4a6ad38f8394238caa0cfdb75f7 Mon Sep 17 00:00:00 2001 From: Andrew Makousky Date: Fri, 7 Aug 2020 03:11:33 -0500 Subject: [PATCH] Comments on BBU functions and signal discipline. --- hardware/fpga/bbu/README.md | 110 ++++++++++++++++++++++++++++++++++-- 1 file changed, 105 insertions(+), 5 deletions(-) diff --git a/hardware/fpga/bbu/README.md b/hardware/fpga/bbu/README.md index ac24664..0e3efd9 100644 --- a/hardware/fpga/bbu/README.md +++ b/hardware/fpga/bbu/README.md @@ -1,10 +1,13 @@ # "BBU" Apple Custom Silicon -The "BBU", as it is called on the Macintosh SE's printed circuit board -silkscreen, is a relatively complex Apple custom silicon chip, -compared to the other custom chips on the Macintosh SE's Main Logic -Board (MLB). Despite its intimidating look as a chip with a huge -number of pins, its purpose can be summarized as follows. +The "BBU" (Bob Bailey Unit), as it is called on the Macintosh SE's +printed circuit board silkscreen, is a relatively complex Apple custom +silicon chip, compared to the other custom chips on the Macintosh SE's +Main Logic Board (MLB). Despite its intimidating look as a chip with +a huge number of pins, its purpose can be summarized as follows. + +* Take the master 16 MHz clock as input and divided it down to + generate the 8 MHz, 3.7 MHz, and 2 MHz clock signals as output. * Provide a single address bus interface to ROM, RAM, and I/O devices, including simple digital I/O pins. @@ -35,3 +38,100 @@ The following I/O chips are connected to the BBU: Other chips that are connected to the BBU are mainly interfaced via only simple, single-pin interfaces. + +---------- + +## More explanation on pin functions + +* `RA0` - `RA9`: Address-multiplexed pins intended to connect directly + to the address lines on the RAM SIMMs. + +* `RA9` is only controlled when the `MBRAM` input is TRUE, i.e. +5V. + This indicates that 1 MB RAM SIMMs are being used. Otherwise, it is + kept at zero and high memory addresses are marked as bus errors. + 256K RAM SIMMs are used in this case. + +* When `ROW2` input is TRUE, i.e. +5V, it indicates that both RAM SIMM + rows are in use. Otherwise, only the first row of RAM SIMM is used + and high addresses are marked as bus errors. + +* If both `MBRAM` and `ROW2` are TRUE, i.e. +5V, it is also possible + for the BBU to detect a 2.5 MB RAM configuration and adjust bus + errors flagging accordingly. + +* `RDO0` - `RDO15` are bidirectional data signals, they are the + primary means by which single-pin I/O devices and the like are + mapped into the address space that can be directly accessed by the + CPU, in conjunction with the address inputs. + +* I do not know if the C8M and C3.7M clock signals are inputs or + outputs. The master clock crystal is C16M, 16 MHz, generated by the + "FOX" crystal oscillator on the MLB. If the clock frequency is + divided down by the BBU, then these are outputs. In any case, C16M + is definitely an input. + + Please note: The "F" suffixes is a good hint saying that a signal is + "filtered," which only happens after a signal has already been + output from the primary device. So, if you are connecting to an "F" + signal, that means you're an input. Otherwise, you're an output. + + Therefore, that's pretty strong evidence that the lower frequency + clock signals are divided down by the BBU. + +* All peripheral/device chip select/enable signals are output signals. + +* MC68000 output signals directly connected to the BBU are BBU input + signals. + +* Output signals that connect to MC68000 inputs: `*DTACK`, `*BERR`, + `*IPL0`, `*IPL1`, `*IPL2`, `*VPA`. + +* Is `*RES` an input only? I would assume so, assuming there is + another, dedicated circuit to control hard board resets. Note that + the PDS bus connector ties the `*HALT` and `*RES` signals together. + So, if the MC68000 CPU executes a `RESET` instruction, that won't + just reset all peripheral devices, but it will also reset the CPU + itself. + +* I'm assuming `*PMCYC` is an output signal? It only connects to the + PDS slot and the F257 chips. + +---------- + +Peripheral device signals, input or output? + +* `*ENTD1K` is very likely an input signal, for PDS use. Why? The + Macintosh Classic is essentially a stripped-down Macintosh SE that + uses the same BBU. In that schematic, pin 11 is indicated as + connected to a pull-up resistor. So, clearly this must be an input + since it cannot be connected. + +* `*EAREN` is very likely an output signal (also for PDS use), for the + reason it is not indicated in the Bomarc Macintosh Classic + schematics, i.e. it could be disconnected entirely. + +* Output signals: `*SCCRD`, `*PWM`?, `*DACK`, `SND`, + `VIDPG2`, `*VSYNC`, `*HSYNC`, `VIDOUT`. + +* Output SELECT signals: `IWM`, `*SCCEN`. `VIA.CS1`. + +* Output RESET signals: `SNDRES`. + +* Input signals: `SCSIDRQ`, `VIAIRQ`. + +---------- + +There is still more to learn/investigate relating to unspecified +signals. + +---------- + +## Ideas for Enhancements + +* Auto-detect jumper settings for RAM by testing for address + wrap-around. Unfortunately, because the CPU `HALT` and `RESET` are + wired together, this probably requires circuit board changes to + function successfully. + +* Add Memory Manager Unit (MMU) functionality to implement virtual + memory.