Commit work-in-progress.
Some improvements made on accuracy of circuit descriptions.
This commit is contained in:
Andrew Makousky
parent
6a74bb5a13
commit
b957f0cb84
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@ -90,8 +90,8 @@ a huge number of pins, its purpose can be summarized as follows.
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Also, note that the address multiplexing is configured as follows:
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Row access strobe: A1, A11, A12, A13, A14, A15, A16, RA7*, A18, RA9*.
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Column access strobe: A2, A3, A4, A5, A6, A7, A8, RA7*, A10, RA9*.
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Row access strobe: A2, A3, A4, A5, A6, A7, A8, RA7*, A10, RA9*.
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Column access strobe: A1, A11, A12, A13, A14, A15, A16, RA7*, A18, RA9*.
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RA7 and RA9 are controlled directly by the BBU rather than being
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wired through the F257 address multiplexers. Now, the devil is in
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@ -107,18 +107,29 @@ a huge number of pins, its purpose can be summarized as follows.
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configuration of one row of DRAM SIMMs, this means you can configure
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a Macintosh SE with only 128K of RAM. Hilarious!
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If only 256K RAM SIMMs are installed, then RA7 is either A17 (row)
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or A9 (column). RA9 is not used. If there are two rows of DRAM
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If only 256K RAM SIMMs are installed, then RA7 is either A9 (row) or
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A17 (column). RA9 is not used. If there are two rows of DRAM
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SIMMs, A19 is used to determine which one to use.
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If 1MB RAM SIMMs are installed, then RA7 is either A17 (row) or A9
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(column). RA9 is either A20 (row) or A19 (column). If there are
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If 1MB RAM SIMMs are installed, then RA7 is either A9 (row) or A17
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(column). RA9 is either A19 (row) or A20 (column). If there are
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two rows of DRAM SIMMs, A21 is used to determine which one to use.
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Since RAM accesses are always on even bytes in 16-bit quantities, A0
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is implied to be zero and therefore also is not available on the
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CPU.
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The purpose of this weird scrambled address mapping is to satisfy
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two goals:
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1. To allow the framebuffer scanning circuitry to double as DRAM
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refresh.
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2. To enable fast-page mode (FPM) for fetching two 16-bit words in
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sequence (one "longword"). This in turn reduces the BBU's
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memory access overhead and therefore increases the speed of CPU
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memory accesses.
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* So, wow. Here's a list of all possible Macintosh SE RAM
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configurations.
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@ -230,34 +230,6 @@ module bbu_master_ctrl
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// Installed RAM size.
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wire [23:0] ramsz;
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// SCSI support: Handle chip select, and handle DMA. Important!
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// Never have *DACK and *SCSI active simultaneously. Okay, so
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// let's get this straight. When we would normally assert *DTACK,
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// we release *SCSI and wait for SCSI.DRQ. Then when we receive
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// it, we can assert *DTACK and also *DACK, with a timer to
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// deassert *DACK. Important! Make sure we do not go faster than
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// the minimum read/write pulse width of the SCSI chip.
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// Important! How to handle SCSI DMA... according to Guide to the
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// Macintosh family hardware, page 126, this is "pseudo-DMA" mode.
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// The BBU does not assert `*DTACK` until `SCSIDRQ` is received to
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// indicate the DMA transfer is complete. And again, noting from
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// page 126, . Likewise, `*DTACK` is asserted for all addresses in
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// range, even if nothing is mapped. No stringent bus error
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// control here, that's a hobbyist extension. And again, inded
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// `*DTACK` is tri-stated according to the manual when `*EXTDTK`
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// (`*EXT.DTACK`) is asserted.
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// TODO: How do we know if DMA mode is true? Do we have to snoop
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// the address but to get this information.
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// Now, here's the golden rule: "If any access has not terminated
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// within 265 ms, the BBU asserts the bus error signal /BERR."
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// There you go, that's how it is driven, though the condition only
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// happens for PDS and SCSI accesses. So, another thing,
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// yes... there must be at least a nominal delay to assert `*DTACK`
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// to allow PDS cards to intervene by asserting `*EXTDTK` first.
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// TODO MOVE DOCUMENTATION: PLEASE NOTE, PDS cards can also access
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// DRAM, not just the CPU. This is mainly a matter of bus
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// arbitration, then as far s the BBU is concerned, PDS access to
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@ -668,12 +640,6 @@ endmodule
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* 0xf00000 - 0xffffef: ??? (the ROM appears to be accessing here)
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* 0xfffff0 - 0xffffff: Auto Vector
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TODO FIXME: Note that SCSI chip enable is NOT asserted when A9 is
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one, and Macintosh Plus asserts DACK when A9 is one, but not when
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it is zero. Okay, so I think I have that figured out. Add 512 for
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DMA mode access logic, otherwise we do not implement DMA access
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mode at all.
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This address map has also been confirmed with Guide to the
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Macintosh family hardware, page 127. PLEASE NOTE: In SCC Read
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zone, if A0 == 1, then that is an SCC RESET. IWM must be A0 == 1,
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@ -697,40 +663,6 @@ endmodule
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overflow accesses should just wrap around and repeat access to the
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same RAM.
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PLEASE NOTE: Guide to the Macintosh family hardware, page 122. "A
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word-wide access to any SCC address causes a phase shift in the
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processor clock, and is used by the operating system to correct the
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phase when necessary."
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"At system startup, the operating system reads an address in the
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range $F0 0000 through $F7 FFFF (labeled _Phase read_ in Gifgures
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3-1 and 3-2) to determine whether the computer's high-frequency
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timing signals are correctly in phase. When the timing signals are
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not in phase, RAM accesses are not timed correctly, causing an
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unstable video display, RAM errors, and VIA errors." Well, I can
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see how that would be happening with just a bunch of PALs, but I
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don't think it still needs to be that way when you have the BBU in
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charge, you can do better! And indeed, that note only appears to
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apply to the Macintosh Plus, not the Macintosh SE, as it is listed
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in that section.
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But, for the sake of Macintosh Plus recreation, please note. The
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TSG PAL places one of the high-frequency phase indicator signals on
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D0 of the address bus, I assume it is the 1 MHz *PMCYC signal. A
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multiple address read instruction is used to read three consecutive
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data values from the address bus in synchronous I/O mode (due to
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using address 0xf00000), so each address read is either 10 or 20
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CPU cycles long. This will sample the phase at a few different
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points. The phase readings are added together, if they are zero or
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one, then we are "in-phase." Otherwise, phase readings 2 and 3 are
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considered "out-of-phase" so we access a word-width address in the
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SCC range to shift the high frequency timing by 128 ns (one CPU
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clock cycle at 8 MHz).
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The important thing to remember is that every MC68000 instruction
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executes for an even number of clock cycles (divisible by 2), and
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there is no pipelining in these early CPUs.
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TODO FIXME: Guide to the Macintosh family hardware, page 127.
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Okay, so this is how to interpret the information about the
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boot-time overlay for the alternate RAM location. Only a 2MB zone
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@ -744,15 +676,47 @@ endmodule
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I don't really quite understand, though, sorry. Okay, this means,
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the first row, right? "If 2.5 or 4 MB only upper row is
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accessible" page 127.
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The signal *VPA is asserted in address range 0xe00000 - 0xffffff,
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optionally excluding invalid addresses when a bus error signal is
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generated. This is for synchronous I/O devices accessed in the old
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6800 fashion.
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----------
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But, for the sake of Macintosh Plus recreation, please note.
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Guide to the Macintosh family hardware, page 122. For the
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Macintosh Plus: "A word-wide access to any SCC address causes a
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phase shift in the processor clock, and is used by the operating
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system to correct the phase when necessary."
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"At system startup, the operating system reads an address in the
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range $F0 0000 through $F7 FFFF (labeled _Phase read_ in figures
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3-1 and 3-2) to determine whether the computer's high-frequency
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timing signals are correctly in phase. When the timing signals are
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not in phase, RAM accesses are not timed correctly, causing an
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unstable video display, RAM errors, and VIA errors." Well, I can
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see how that would be happening with just a bunch of PALs, but I
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don't think it still needs to be that way when you have the BBU in
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charge, you can do better! And indeed, that note only appears to
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apply to the Macintosh Plus, not the Macintosh SE, as it is listed
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in that section.
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The TSG PAL places one of the high-frequency phase indicator
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signals on D0 of the address bus, I assume it is the 1 MHz *PMCYC
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signal. A multiple address read instruction is used to read three
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consecutive data values from the address bus in synchronous I/O
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mode (due to using address 0xf00000), so each address read is
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either 10 or 20 CPU cycles long. This will sample the phase at a
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few different points. The phase readings are added together, if
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they are zero or one, then we are "in-phase." Otherwise, phase
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readings 2 and 3 are considered "out-of-phase" so we access a
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word-width address in the SCC range to shift the high frequency
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timing by 128 ns (one CPU clock cycle at 8 MHz).
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The important thing to remember is that every MC68000 instruction
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executes for an even number of clock cycles (divisible by 2), and
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there is no pipelining in these early CPUs.
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*/
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module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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n_sccen, n_sccrd, n_iow, n_iwm, via_cs1, n_vpa,
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n_berr, n_as, a23_19, berr_ram, n_extdtk,
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module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi, scsidrq,
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n_dack, n_sccen, n_sccrd, n_iow, n_iwm, via_cs1,
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n_vpa, n_berr, n_as, a23_19, a9, n_extdtk,
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boot_overlay, r_n_w, reg_romen, reg_ram_w,
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n_dtack_peri);
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input wire n_res;
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@ -760,6 +724,8 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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output wire n_ramen;
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output wire n_romen;
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output wire n_scsi;
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input wire scsidrq;
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output wire n_dack;
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output wire n_sccen;
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output wire n_sccrd;
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output wire n_iow;
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@ -769,7 +735,7 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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output wire n_berr;
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input wire n_as;
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input wire [4:0] a23_19;
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input wire berr_ram; // Would this RAM address be a bus error?
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input wire a9;
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input wire n_extdtk;
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input wire boot_overlay;
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input wire r_n_w;
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@ -781,14 +747,14 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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output wire n_dtack_peri; // *DTACK for peripherals
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wire reg_ram, reg_ram_r;
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wire scdma; // host requested performing a SCSI pseudo-DMA read/write
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wire scsi, sccrd, sccwr;
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wire berr_scc;
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wire n_dtack_peri_pt; // *DTACK peripherals "pre-trigger"
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reg n_dtack_peri_bf; // *DTACK for peripherals buffer
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reg [31:0] berr_cntr; // Counter to trigger `*BERR` after 265 ms
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// If the boot-time overlay is enabled but we attempt to write to
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// the regular RAM region, then this is a *RAMEN trigger. The
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// the regular RAM region, then this is a `*RAMEN` trigger. The
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// overlay control logic will zero the switch on the next cycle,
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// but we use combinatorial logic here to act immediately.
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assign reg_ram = ~n_as & (a23_19[4:3] == 2'b00);
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@ -799,10 +765,19 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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(a23_19[4:1] == 4'h7))) | reg_ram_w) :
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reg_ram);
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assign reg_romen = ~n_as & (a23_19[4:1] == 4'h4);
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// Only trigger *ROMEN for reads, not writes, in overlay zone.
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// Only trigger `*ROMEN` for reads, not writes, in overlay zone.
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assign n_romen = ~(reg_romen | (boot_overlay & reg_ram_r));
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assign scsi = ~n_as & (a23_19[4:0] == 5'b01011);
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assign n_scsi = ~scsi;
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// Note that the SCSI chip enable is NOT asserted in pseudo-DMA
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// access mode, which is indicated by A9 (add decimal 512 to base
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// address).
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assign scdma = scsi & a9;
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// assign n_scsi = ~(scsi & ~scdma);
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assign n_scsi = ~(scsi & ~a9); // simplification
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// N.B.: One idea I had was to use a timer to de-assert `*DACK` to
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// ensure it is not held too long. For now I am assuming this is
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// not necessary given the MC68000 address bus speed.
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assign n_dack = scdma & scsidrq;
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assign sccrd = ~n_as & (a23_19[4:1] == 4'h9);
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assign sccwr = ~n_as & (a23_19[4:1] == 4'hb);
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assign n_sccen = ~(sccrd | sccwr);
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@ -810,7 +785,11 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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assign n_iow = ~((scsi & ~r_n_w) | sccwr);
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assign n_iwm = ~(~n_as & (a23_19[4:1] == 4'hd));
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assign via_cs1 = ~n_as & (a23_19[4:0] == 5'b11101);
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assign n_vpa = ~(via_cs1 | (~n_as & (a23_19[4:1] == 4'hf)));
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// The signal *VPA is asserted in address range 0xe00000 -
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// 0xffffff. This is for synchronous I/O devices accessed in the
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// old 6800 fashion.
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assign n_vpa = ~(~n_as & ((a23_19[4:1] == 4'he) |
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(a23_19[4:1] == 4'hf)));
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// N.B.: According to Guide to the Macintosh family hardware, page
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// 126, the implementation of Auto Vector is easy and
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// straightforward for the BBU. Just assert `*VPA` in the address
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@ -822,19 +801,12 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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// write-only SCC address space, and vice versa.
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assign berr_scc = (sccrd & ~r_n_w) | (sccwr & r_n_w);
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// Note that if the PDS card asserts *EXTDTK, we also must not
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// drive *BERR. TODO EVALUATE: Should we wait a cycle before
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// asserting *BERR to give the PDS card time to respond first?
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assign n_berr = n_as | ~n_extdtk |
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~((~n_ramen & berr_ram) |
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berr_scc |
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(a23_19[4:0] == 5'b01010) |
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(a23_19[4:1] == 4'h7) |
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(a23_19[4:1] == 4'h8) |
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(a23_19[4:1] == 4'ha) |
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(a23_19[4:1] == 4'hc) |
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(a23_19[4:0] == 5'b11100));
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// TODO: Also flag bus errors for the final address zone.
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// Here's the rule on asserting `*BERR`, Guide to the Macintosh
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// Family hardware, page 126: "If any access has not terminated
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// within 265 ms, the BBU asserts the bus error signal /BERR." In
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// practice, this would possibly only occur for PDS and SCSI
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// accesses.
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assign n_berr = ~(berr_cntr >= 4240000);
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// NOTE: For all peripherals, we must set `*DTACK` from the BBU
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// upon successful access condition and time durations because it
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@ -845,25 +817,30 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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// N.B.: According to Guide to the Macintosh family hardware,
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// `*DTACK` is not used to respond to addresses in the range
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// 0xe00000 - 0xffffff, only below that. `*VPA` alone is used to
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// respond to these addresses. So therefore, we exclude `VIA.CS1`.
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assign n_dtack_peri_pt = n_scsi & n_sccen & n_iwm;
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// N.B. We use combinatorial logic here to deassert *DTACK for
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// peripherals as soon as *AS is released.
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assign n_dtack_peri = n_as | n_dtack_peri_bf;
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// respond to these addresses. Except for the case of SCSI
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// pseudo-DMA accesses, we only assert `*DTACK` when we assert
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// `*DACK`.
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assign n_dtack_peri = n_as | ((n_vpa | scdma) & n_dack);
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// N.B. For now, we leave it to higher level logic to put on
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// `*DTACK` on high-impedance when `*EXTDTK` is asserted.
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// assign n_dtack_peri =
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// n_extdtk ? (n_as | ((n_vpa | scdma) & n_dack)) : 'bz;
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always @(negedge n_res) begin
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n_dtack_peri_bf <= 1;
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berr_cntr <= 0;
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end
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always @(posedge clk) begin
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if (n_res) begin
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if (n_as)
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n_dtack_peri_bf <= 1;
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berr_cntr <= 0;
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else begin
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if (n_dtack_peri_pt)
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n_dtack_peri_bf <= 0;
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if (berr_cntr < 4240000) // # of 16 MHz pulses in 265 ms
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berr_cntr <= berr_cntr + 1;
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else
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n_dtack_peri_bf <= 1;
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; // Nothing to be done.
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end
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end
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else
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@ -871,38 +848,6 @@ module decode_devaddr (n_res, clk, n_ramen, n_romen, n_scsi,
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end
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endmodule
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// Determine if a RAM address is out of range and should therefore
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// signal a bus error.
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module berr_ram_logic (a0_21, ramsz, /*ramsz_en,*/ berr_ram);
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input wire [21:0] a0_21;
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input wire [23:0] ramsz;
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// input wire [6:0] ramsz_en;
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output wire berr_ram;
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// We could either use arithmetic comparison (easiest to code in
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// Verilog), or bit-wise comparisons (possibly more efficient in
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// hardware). We may simply consider implementing this logic in a
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// separate module.
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// 4MB valid: 0x000000 - 0x3fffff
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// 4MB invalid: None!
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// 2.5MB valid: 0x000000 - 0x27ffff
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// 2.5MB invalid: 0x280000 - 0x3fffff
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// 2MB valid: 0x000000 - 0x1fffff
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// 2MB invalid: 0x200000 - 0x3fffff
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// 1MB valid: 0x000000 - 0x0fffff
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// 1MB invalid: 0x100000 - 0x3fffff
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// 512K valid: 0x000000 - 0x07ffff
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// 512K invalid: 0x080000 - 0x3fffff
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// 256K valid: 0x000000 - 0x03ffff
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// 256K invalid: 0x040000 - 0x3fffff
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// 128K valid: 0x000000 - 0x01ffff
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// 128K invalid: 0x020000 - 0x3fffff
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||||
// N.B. Verilog comparison is unsigned by default.
|
||||
assign berr_ram = { 1'b0, a0_21[21:17] } < ramsz[22:17];
|
||||
endmodule
|
||||
|
||||
// Boot-time memory overlay register and controlling logic. This is
|
||||
// fairly straightforward to implement once you see all the other
|
||||
// logic of the BBU in place.
|
||||
|
|
@ -959,6 +904,7 @@ endmodule
|
|||
|
||||
// RA7/RA9 selector logic. Determine which CPU address pins should be
|
||||
// routed to these RAM address pins based off of the installed RAM.
|
||||
// TODO FIXME: This is incorrect in light of new knowledge.
|
||||
module dramctl_ra7_9 (ra7, ra9, cas_n_ras, row2, mbram, s64kram,
|
||||
a9, a17, a19, a20, a10);
|
||||
output wire ra7;
|
||||
|
|
@ -1551,7 +1497,7 @@ endmodule
|
|||
/* TODO: Summary of what is missing and left to implement: DRAM
|
||||
initialization pulses, DRAM refresh, detect 2.5MB of RAM and
|
||||
configure address buffers accordingly, video, disk, and audio
|
||||
scanout, SCSI DMA, EXTDTK yielding.
|
||||
scanout, EXTDTK yielding.
|
||||
|
||||
Okay, so the VERDICT on DRAM initialization pulses. We don't
|
||||
actually use these as we should, strictly speaking, but why does it
|
||||
|
|
@ -1602,8 +1548,16 @@ So, how many longwords for the video framebuffer?
|
|||
In hex: 0x1560
|
||||
Number of address bits fully covered by a full scan: 12
|
||||
|
||||
Okay, so the question, does it work for DRAM refresh? Indeed it
|
||||
does! Well, at least for <=1MB of RAM.
|
||||
Okay, so the question, does it work for DRAM refresh? Indeed it does!
|
||||
Well, the number of longwords swept is great enough to cover all DRAM
|
||||
rows for 4MB of RAM, but the address bit mapping appears only to work
|
||||
for <=1MB of RAM.
|
||||
|
||||
Please note that since we use only a single row access strobe signal
|
||||
for both DRAM rows and instead use separate column access strobes to
|
||||
differentiate between the rows, even if all the video memory addresses
|
||||
are only in one row, we still refresh the other row as long as we
|
||||
cover all the row addresses.
|
||||
|
||||
RA9 looks to be trouble. But, the Unitron reverse engineering docs
|
||||
almost have a solution. Set this to A17 (?) and it should "just work"
|
||||
|
|
|
|||
Loading…
Reference in New Issue