Documentation updates.

hardware/fpga/bbu/README.md

@@ -45,7 +45,8 @@ a huge number of pins, its purpose can be summarized as follows.
     * 0xfffff0 - 0xffffff: Auto Vector
 
   The Macintosh SE goes a step further and adds invalid address guard
-  zones around the SCC and IWM mappings:
+  zones around the SCC and IWM mappings... these are simply available
+  for use by PDS expansion cards:
 
     * 0x000000 - 0x3fffff: RAM/ROM (switches based on overlay)
     * 0x400000 - 0x4fffff: ROM
@@ -218,17 +219,17 @@ DRAM.  Guide to the Macintosh family hardware, page 84.
 
 * `RA9` is only controlled when the `MBRAM` input is TRUE, i.e. +5V.
   This indicates that 1MB RAM SIMMs are being used.  Otherwise, it is
-  kept at zero and high memory addresses are marked as bus errors.
-  256K RAM SIMMs are used in this case.
+  kept at zero and high memory addresses wrap around.  256K RAM SIMMs
+  are used in this case.
 
 * When `ROW2` input is TRUE, i.e. +5V, it indicates that both RAM SIMM
   rows are in use.  Otherwise, only the first row of RAM SIMM is used
-  and high addresses are marked as bus errors.  And, `CAS1L` and
-  `CAS1H` are not driven.
+  and high addresses wrap around.  And, `CAS1L` and `CAS1H` are not
+  driven.
 
 * If both `MBRAM` and `ROW2` are TRUE, i.e. +5V, it is also possible
-  for the BBU to detect a 2.5MB RAM configuration and adjust bus
-  errors flagging accordingly.
+  for the BBU to detect a 2.5MB RAM configuration and address
+  wrap-around will change accordingly.
 
 * `RDQ0` - `RDQ15` are bidirectional data signals, they are the
   primary means by which single-pin I/O devices and the like are
@@ -236,28 +237,25 @@ DRAM.  Guide to the Macintosh family hardware, page 84.
   CPU, in conjunction with the address inputs.  Namely, the BBU reads
   and writes to RAM, and the CPU accesses that RAM on its own time.
 
-* I do not know if the C8M and C3.7M clock signals are inputs or
-  outputs.  The master clock crystal is C16M, 16 MHz, generated by the
-  "FOX" crystal oscillator on the MLB.  If the clock frequency is
-  divided down by the BBU, then these are outputs.  In any case, C16M
-  is definitely an input.
+* The C8M and C3.7M clock signals are outputs.  The master clock
+  crystal is C16M, 16 MHz, generated by the "FOX" crystal oscillator
+  on the MLB.  C16M is an input to the BBU.
 
   Please note: The "F" suffixes is a good hint saying that a signal is
   "filtered," which only happens after a signal has already been
   output from the primary device.  So, if you are connecting to an "F"
   signal, that means you're an input.  Otherwise, you're an output.
 
-  Therefore, that's pretty strong evidence that the lower frequency
-  clock signals are divided down by the BBU.
-
 * All peripheral/device chip select/enable signals are output signals.
 
 * MC68000 output signals directly connected to the BBU are BBU input
   signals.  Namely: `*LDS`, `*UDS`, `R/*W`, `*AS`.
 
 * Output signals that connect to MC68000 inputs: `*DTACK`, `*BERR`,
-  `*IPL0`, `*IPL1`, `*IPL2`, `*VPA`.  Or are the interrupt signals BBU
-  inputs?
+  `*IPL0`, `*VPA`.
+
+* `*IPL1` is an input, it is generated by the SCC and the BBU yields
+  to it if necessary by not generating `*IPL0`.
 
 * Is `*RES` an input only?  I would assume so, assuming there is
   another, dedicated circuit to control hard board resets.  Note that
@@ -267,22 +265,29 @@ DRAM.  Guide to the Macintosh family hardware, page 84.
   itself.
 
   Note that the BBU needs a RESET input pin for its own sake since it
-  includes sequential logic to scan the CRT and sound buffers.
+  includes sequential logic to scan the CRT and sound buffers.  BUT,
+  this is the key to remember: if you hold down the programmer's reset
+  button on a Macintosh computer, that doesn't cause the CRT to blank
+  out to black.  That's how we know the BBU only relies on an internal
+  power-on reset for at least for some circuits.  Other circuits like
+  the ROM overlay switch are reset by the external reset too.
 
 * `C2M` is an output signal, it primarily controls the address
   multiplexers to select either the row address (zero) or column
-  address (one).  Connecting directly to a simple 2 MHz clock could be
-  adequate, or a more tailored method may be used for higher
-  performance and lower memory access time.
+  address (one).  Older Macintoshes connected directly to a 2 MHz
+  signal, but this is actually a misnomer in the case of the Macintosh
+  SE because is uses a more tailored approach for higher performance
+  through the use of DRAM Fast Page Mode (FPM).
 
 * `*PMCYC` is an output signal.  Its primary conceptual purpose is to
   define "whose turn" it is to access DRAM, the CPU or the BBU?  In
-  the Macintosh Plus, this was a simple 1 MHz clock, since the CPU
-  always takes a multiple of 4 clock cycles at 8 MHz to access DRAM.
-  But the Macintosh SE uses a more sophisticated pattern to give the
-  CPU as large of a time share as possible to access DRAM.  The symbol
-  is probably short for Processor Memory CYCle.  It only connects to
-  the PDS slot and the F257 chips.
+  the Macintosh Plus, this was a simple 1 MHz clock (that was masked
+  during the vertical blanking interval), since the CPU always takes a
+  multiple of 4 clock cycles at 8 MHz to access DRAM.  But the
+  Macintosh SE uses a more sophisticated pattern to give the CPU as
+  large of a time share as possible to access DRAM.  The symbol is
+  probably short for Processor Memory CYCle.  It only connects to the
+  PDS slot and the F257 chips.
 
 ----------
 
@@ -312,8 +317,8 @@ Peripheral device signals, input or output?
   we don't need to actually implement this signal because it is marked
   as "reserved" in the PDS slot documentation.
 
-* Output signals: `*SCCRD`, `*PWM`?, `*DACK`, `SND`,
-  `*VSYNC`, `*HSYNC`, `VIDOUT`.
+* Output signals: `*SCCRD`, `*PWM`, `*DACK`, `SND`, `*VSYNC`,
+  `*HSYNC`, `VIDOUT`.
 
 * Output SELECT signals: `IWM`, `*SCCEN`. `VIA.CS1`.
 

hardware/fpga/bbu/bbu.v

@@ -568,7 +568,8 @@ endmodule
  
    These are the particular address zones for Macintosh SE, according
    to MESS/MAME source code.  In particular, SCC and IWM are
-   surrounded with invalid address guard zones:
+   surrounded with invalid address guard zones... these are simply
+   available for use by PDS expansion cards:
 
    * 0x000000 - 0x3fffff: RAM/ROM (switches based on overlay)
    * 0x400000 - 0x4fffff: ROM