133 lines
3.4 KiB
Verilog
133 lines
3.4 KiB
Verilog
`timescale 1ns/100ps
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`include "mac128pal.v"
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`include "test_stdlogic.v"
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module test_palcl();
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wire vcc, gnd;
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reg n_res;
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reg clock;
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reg simclk;
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wire sysclk, pclk, p0q1, clkscc, p0q2, vclk, q3, q4;
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reg e, keyclk;
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reg [23:0] a;
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reg n_as, n_uds, n_lds;
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wire n_dtack;
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reg r_n_w;
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wire [15:0] d;
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wire casl, cash, ras, we;
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wire [9:0] ra;
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wire [15:0] rdq;
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reg n_intscc, n_intvia;
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wire n_ipl0;
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wire n_ramen, n_romen, n_csiwm, n_sccrd, n_cescc, n_vpa;
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wire viapb6;
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reg ovlay;
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wire viacb1;
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reg n_sndpg2, n_vidpg2;
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wire n_vsync, n_hsync, vid;
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assign vcc = 1;
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assign gnd = 0;
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palcl u0_palcl(simclk, vcc, gnd, n_res, clock,
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sysclk, pclk, p0q1, clkscc, p0q2, vclk, q3, q4,
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e, keyclk,
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a[23], a[22], a[21], a[20], a[19], a[18], a[17], a[16],
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a[15], a[14], a[13], a[12], a[11], a[10], a[9],
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a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1],
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n_as, n_uds, n_lds, n_dtack, r_n_w,
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d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7],
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d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15],
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casl, cash, ras, we,
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ra[0], ra[1], ra[2], ra[3], ra[4], ra[5], ra[6], ra[7],
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ra[8], ra[9],
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rdq[0], rdq[1], rdq[2], rdq[3], rdq[4], rdq[5], rdq[6],
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rdq[7], rdq[8], rdq[9], rdq[10], rdq[11], rdq[12], rdq[13],
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rdq[14], rdq[15],
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n_intscc, n_intvia, n_ipl0,
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n_ramen, n_romen, n_csiwm, n_sccrd, n_cescc, n_vpa,
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viapb6, ovlay, viacb1, n_sndpg2, n_vidpg2,
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n_vsync, n_hsync, vid);
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// Trigger RESET at beginning of simulation. Make sure there is an
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// initial falling edge.
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initial begin
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n_res = 1;
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#2 n_res = 0;
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#18 n_res = 1;
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end
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// Initialize clock.
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initial begin
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clock = 0;
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simclk = 0;
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e = 0;
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keyclk = 0;
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end
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// 64 unit clock cycle (~16MHz).
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always
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#32 clock = ~clock;
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// ~1MHz 6800 E clock
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always begin
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#768 e = 1; // 6 CPU clocks low
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#512 e = 0; // 4 CPU clocks high
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end
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// Sub-cycle simulator clock triggers as fast as possible.
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// N.B.: This is now disabled as it has been vetted that Verilog is
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// designed to simulate self-referential combinatorial logic
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// equations just fine. Disabling this helps speed up the
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// simulation.
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// always
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// #1 simclk = ~simclk;
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// Initialize all other control inputs.
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initial begin
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a <= 0;
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n_as <= 1; n_uds <= 1; n_lds <= 1; r_n_w <= 1;
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n_intscc <= 1; n_intvia <= 1; ovlay <= 1;
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n_sndpg2 <= 1; n_vidpg2 <= 1;
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end
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endmodule
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module test_mac128pal();
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// Instantiate individual test modules.
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test_ls161 tu0_ls161();
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test_ls245 tu1_ls245();
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test_palcl tu2_palcl();
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// Perform the remainder of global configuration here.
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// Set simulation time limit.
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initial begin
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// #1920000 $finish;
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// PLEASE NOTE: We must simulate LOTS of cycles in order to see
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// what the oscilloscope trace for one video frame looks like.
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#30720000 $finish;
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end
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// We can use `$display()` for printf-style messages and implement
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// our own automated test suite that way if we wish.
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initial begin
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$display("Example message: Start of simulation. ",
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"(time == %1.0t)", $time);
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end
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// Log to a VCD (Variable Change Dump) file.
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initial begin
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// $dumpfile("test_mac128pal.vcd");
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// Use LXT instead since it is more efficient.
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$dumpfile("test_mac128pal.lxt");
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$dumpvars;
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end
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endmodule
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