16 lines
485 B
Systemverilog
16 lines
485 B
Systemverilog
`ifndef COMMON_VH
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`define COMMON_VH
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// Special type indicator for simclk: it will not be present in
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// physical builds.
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`define virtwire wire
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// Simulate an output wire by using multi-cycle registered logic.
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`define simwire reg
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// Tristate output (output With high-impedance (Z))
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`define output_wz inout
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// To preserve pin numbering at the I/O connections, power wires can
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// be implemented as inputs: constant value 1 for Vcc, 0 for GND.
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`define power input
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`endif // not COMMON_VH
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