32 lines
707 B
Verilog
32 lines
707 B
Verilog
`timescale 1ns/100ps
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`include "mac128pal.v"
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`include "test_stdlogic.v"
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module test_mac128pal();
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// Instantiate individual test modules.
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test_ls161 tu0();
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test_ls245 tu1();
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// Perform the remainder of global configuration here.
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// Set simulation time limit.
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initial begin
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#480 $finish;
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end
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// We can use `$display()` for printf-style messages and implement
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// our own automated test suite that way if we wish.
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initial begin
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$display("Example message: Start of simulation. ",
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"(time == %1.0t)", $time);
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end
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// Log to a VCD (Variable Change Dump) file.
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initial begin
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$dumpfile("test_mac128pal.vcd");
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$dumpvars;
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end
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endmodule
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