108 lines
2.2 KiB
Verilog
108 lines
2.2 KiB
Verilog
`ifndef TEST_STDLOGIC_V
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`define TEST_STDLOGIC_V
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`include "stdlogic.v"
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module test_ls161();
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wire vcc, gnd;
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reg n_res;
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reg clock;
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reg simclk;
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reg n_clr, n_load, enp, ent;
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reg [3:0] loadvec;
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wire [3:0] outvec;
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wire rco;
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assign vcc = 1;
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assign gnd = 0;
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ls161 u0_ls161(n_clr, clock,
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loadvec[0], loadvec[1], loadvec[2], loadvec[3],
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enp, gnd,
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n_load, ent,
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outvec[3], outvec[2], outvec[1], outvec[0],
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rco, vcc);
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// Trigger RESET at beginning of simulation. Make sure there is an
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// initial falling edge.
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initial begin
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n_res = 1;
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#2 n_res = 0;
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#18 n_res = 1;
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end
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// Initialize clock.
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initial begin
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clock = 0;
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simclk = 0;
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end
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// 10 unit clock cycle.
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always
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#5 clock = ~clock;
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// Sub-cycle simulator clock triggers as fast as possible.
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always
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#1 simclk = ~simclk;
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// Play with input values a bit.
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initial begin
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n_load = 1;
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n_clr = 1;
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loadvec = 4'hc;
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enp = 1;
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ent = 1;
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#2 n_clr = 0;
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#18 n_clr = 1;
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#222 n_load = 0;
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#18 n_load = 1;
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#40 enp = 0;
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#20 enp = 1;
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#40 ent = 0;
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#20 ent = 1;
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end
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endmodule
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module test_ls245();
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wire vcc, gnd;
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reg dir, n_oe, n_oe_a, n_oe_b;
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reg [7:0] drv_a, drv_b;
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wire [7:0] sa, sb; // sense_a, sense_b
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assign vcc = 1;
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assign gnd = 0;
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assign sa = (n_oe_a) ? 8'bz : drv_a;
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assign sb = (n_oe_b) ? 8'bz : drv_b;
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ls245 u0_ls245(dir, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5],
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sa[6], sa[7], gnd, sb[7], sb[6], sb[5], sb[4],
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sb[3], sb[2], sb[1], sb[0], n_oe, vcc);
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// Play with input values a bit.
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initial begin
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dir = 0;
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n_oe = 1;
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n_oe_a = 1;
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n_oe_b = 1;
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drv_a = 0;
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drv_b = 0;
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#10 n_oe = 0;
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#10 n_oe_b = 0;
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#10 drv_b = 8'hc6;
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#10 drv_b = 8'h35;
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#10 n_oe_b = 1; n_oe_a = 0;
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#10 dir = 1;
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#10 drv_a = 8'h7f;
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#10 n_oe_a = 1; n_oe_b = 0; dir = 0;
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#10 n_oe_a = 0; n_oe_b = 1; dir = 1;
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#10 n_oe_b = 0; // Test a conflict condition.
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#10 dir = 0; n_oe_a = 1; // Release the conflict.
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#10 n_oe = 1; n_oe_a = 1; n_oe_b = 1;
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end
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endmodule
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`endif // not TEST_STDLOGIC_V
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