456 lines
13 KiB
Verilog
456 lines
13 KiB
Verilog
/* Implementation of standard logic integrated circuits in Verilog to
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facilitate board-level simulations of glue logic. DIP pinout.
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Written in 2020 by Andrew Makousky
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Public Domain Dedication:
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To the extent possible under law, the author(s) have dedicated all
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copyright and related and neighboring rights to this software to
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the public domain worldwide. This software is distributed without
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any warranty.
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You should have received a copy of the CC0 Public Domain Dedication
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along with this software. If not, see
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<http://creativecommons.org/publicdomain/zero/1.0/>.
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*/
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`ifndef STDLOGIC_V
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`define STDLOGIC_V
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`include "common.vh"
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// F00: Quad NAND gates.
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module f00(s1a, s1b, s1y, s2a, s2b, s2y, gnd,
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s3y, s3b, s3a, s4y, s4b, s4a, vcc);
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input wire s1a, s1b;
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output wire s1y;
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input wire s2a, s2b;
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output wire s2y;
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`power wire gnd;
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output wire s3y;
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input wire s3b, s3a;
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output wire s4y;
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input wire s4b, s4a;
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`power wire vcc;
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assign s1y = ~(s1a & s1b);
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assign s2y = ~(s2a & s2b);
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assign s3y = ~(s3a & s3b);
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assign s4y = ~(s4a & s4b);
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endmodule
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// F02: Quad NOR gates.
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module f02(s1y, s1a, s1b, s2y, s2a, s2b, gnd,
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s3a, s3b, s3y, s4a, s4b, s4y, vcc);
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output wire s1y;
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input wire s1a, s1b;
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output wire s2y;
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input wire s2a, s2b;
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`power wire gnd;
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input wire s3a, s3b;
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output wire s3y;
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input wire s4a, s4b;
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output wire s4y;
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`power wire vcc;
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assign s1y = ~(s1a | s1b);
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assign s2y = ~(s2a | s2b);
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assign s3y = ~(s3a | s3b);
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assign s4y = ~(s4a | s4b);
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endmodule
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// F04: Hex inverters.
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module f04(a0, q0, a1, q1, a2, q2, gnd, q5, a5, q4, a4, q3, a3, vcc);
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input wire a0;
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output wire q0;
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input wire a1;
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output wire q1;
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input wire a2;
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output wire q2;
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`power wire gnd;
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output wire q5;
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input wire a5;
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output wire q4;
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input wire a4;
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output wire q3;
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input wire a3;
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`power wire vcc;
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assign q0 = ~a0;
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assign q1 = ~a1;
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assign q2 = ~a2;
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assign q3 = ~a3;
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assign q4 = ~a4;
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assign q5 = ~a5;
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endmodule
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// F08: Quad AND gates.
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module f08(s1a, s1b, s1y, s2a, s2b, s2y, gnd,
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s3y, s3a, s3b, s4y, s4a, s4b, vcc);
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input wire s1a, s1b;
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output wire s1y;
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input wire s2a, s2b;
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output wire s2y;
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`power wire gnd;
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output wire s3y;
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input wire s3a, s3b;
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output wire s4y;
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input wire s4a, s4b;
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`power wire vcc;
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assign s1y = s1a & s1b;
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assign s2y = s2a & s2b;
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assign s3y = s3a & s3b;
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assign s4y = s4a & s4b;
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endmodule
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// F32: Quad OR gates.
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module f32(s1a, s1b, s1y, s2a, s2b, s2y, gnd,
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s3y, s3a, s3b, s4y, s4a, s4b, vcc);
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input wire s1a, s1b;
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output wire s1y;
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input wire s2a, s2b;
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output wire s2y;
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`power wire gnd;
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output wire s3y;
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input wire s3a, s3b;
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output wire s4y;
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input wire s4a, s4b;
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`power wire vcc;
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assign s1y = s1a | s1b;
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assign s2y = s2a | s2b;
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assign s3y = s3a | s3b;
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assign s4y = s4a | s4b;
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endmodule
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// LS161: 4-bit binary counter.
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// Used to generate sequential video and sound RAM addresses.
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module ls161(n_clr, clk, a, b, c, d, enp, gnd,
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n_load, ent, q_d, q_c, q_b, q_a, rco, vcc);
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input wire n_clr, clk, a, b, c, d, enp;
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`power wire gnd;
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input wire n_load, ent;
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output wire q_d, q_c, q_b, q_a;
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output wire rco;
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`power wire vcc;
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wire [3:0] loadvec = { d, c, b, a };
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reg [3:0] outvec;
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assign rco = (ent & (outvec == 4'hf));
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assign { q_d, q_c, q_b, q_a } = outvec;
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// Clear is asynchronous, so it is not dependent on the clock.
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always @(negedge n_clr) begin
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if (~n_clr) outvec <= 0;
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end
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// N.B. As soon as the rising edge of the clock is detected under
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// the proper conditions, we propagate the incremented value to the
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// output pins. We do not wait until the next rising edge of the
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// clock.
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always @(posedge clk) begin
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if (~n_clr)
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; // Nothing to be done.
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else if (~n_load) outvec <= loadvec;
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else if (enp & ent)
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outvec <= outvec + 1;
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// else Nothing to be done.
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end
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endmodule
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// LS165: 8-bit Parallel In, Serial Out shift register. Very similar
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// to LS166 but *Q_H instead of *CLR and different pinout.
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module ls165(sh_n_ld, clk, e, f, g, h, n_q_h, gnd,
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q_h, ser, a, b, c, d, clk_inh, vcc);
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input wire sh_n_ld, clk, e, f, g, h;
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output wire n_q_h;
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`power wire gnd;
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output wire q_h;
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input wire ser, a, b, c, d, clk_inh;
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`power wire vcc;
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wire n_int_clk = ~(clk_inh | clk);
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reg [7:0] int_reg;
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assign q_h = int_reg[7];
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assign n_q_h = ~q_h;
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// N.B. The '165 chips use asynchronous data loading. Don't
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// confuse with '166! This is actuallly a continuous
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// assignment... but the behavior is externally imperceptible until
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// we change to shift mode, so we simply act on the rising edge of
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// SH/*LD.
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always @(posedge sh_n_ld) begin
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int_reg <= { h, g, f, e, d, c, b, a };
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end
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// N.B. As soon as the falling edge of the clock is detected under
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// the proper conditions, we propagate the shifted value to the
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// output pins. We do not wait until the next falling edge of the
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// clock.
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always @(negedge n_int_clk) begin
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if (sh_n_ld)
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int_reg <= { int_reg[6:0], ser };
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else
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; // Nothing to be done.
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end
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endmodule
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// LS166: 8-bit Parallel In, Serial Out shift register.
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// Used to generate the TTL serial video signal.
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module ls166(ser, a, b, c, d, clk_inh, clk, gnd,
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n_clr, e, f, g, q_h, h, sh_n_ld, vcc);
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input wire ser, a, b, c, d, clk_inh, clk;
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`power wire gnd;
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input wire n_clr, e, f, g;
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output wire q_h;
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input wire h, sh_n_ld;
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`power wire vcc;
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wire n_int_clk = ~(clk_inh | clk);
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reg [7:0] int_reg;
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assign q_h = int_reg[7];
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always @(negedge n_clr)
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int_reg <= 0;
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// N.B. The '166 chips uses synchronous data loading. Don't
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// confuse with '165!
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// N.B. As soon as the falling edge of the clock is detected under
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// the proper conditions, we propagate the shifted value to the
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// output pins. We do not wait until the next falling edge of the
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// clock.
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always @(negedge n_int_clk) begin
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if (n_clr) begin
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if (sh_n_ld)
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int_reg <= { int_reg[6:0], ser };
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else
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int_reg <= { h, g, f, e, d, c, b, a };
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end
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end
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endmodule
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// LS245: Octal bus transceivers.
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// Used to control DRAM access from the CPU data bus.
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module ls245(dir, a1, a2, a3, a4, a5, a6, a7, a8, gnd,
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b8, b7, b6, b5, b4, b3, b2, b1, n_oe, vcc);
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input wire dir;
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inout wire a1, a2, a3, a4, a5, a6, a7, a8;
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`power wire gnd;
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inout wire b8, b7, b6, b5, b4, b3, b2, b1;
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input wire n_oe;
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`power wire vcc;
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// (~dir) => (ax <= bx), (dir) => (bx <= ax)
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// N.B. `assign` implements diode isolation to enforce a
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// directional output drive, so we can't assemble bi-directional
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// bit vectors for more compact code in that fashion. `alias` from
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// System Verilog would make that possible, though. Though we
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// could define a sub-module to use bit vectors, it turns out that
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// consumes just as many lines of code. So we just go repetitive.
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assign a1 = (n_oe | dir) ? 8'bz : b1;
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assign a2 = (n_oe | dir) ? 8'bz : b2;
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assign a3 = (n_oe | dir) ? 8'bz : b3;
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assign a4 = (n_oe | dir) ? 8'bz : b4;
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assign a5 = (n_oe | dir) ? 8'bz : b5;
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assign a6 = (n_oe | dir) ? 8'bz : b6;
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assign a7 = (n_oe | dir) ? 8'bz : b7;
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assign a8 = (n_oe | dir) ? 8'bz : b8;
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assign b1 = (n_oe | ~dir) ? 8'bz : a1;
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assign b2 = (n_oe | ~dir) ? 8'bz : a2;
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assign b3 = (n_oe | ~dir) ? 8'bz : a3;
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assign b4 = (n_oe | ~dir) ? 8'bz : a4;
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assign b5 = (n_oe | ~dir) ? 8'bz : a5;
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assign b6 = (n_oe | ~dir) ? 8'bz : a6;
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assign b7 = (n_oe | ~dir) ? 8'bz : a7;
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assign b8 = (n_oe | ~dir) ? 8'bz : a8;
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endmodule
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// F138: 3-to-8 line decoder/demultiplexer, active low.
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module f138(a0, a1, a2, n_e1, n_e2, e3, n_y7, gnd,
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n_y6, n_y5, n_y4, n_y3, n_y2, n_y1, n_y0, vcc);
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input wire a0, a1, a2, n_e1, n_e2, e3;
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output wire n_y7;
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`power wire gnd;
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output wire n_y6, n_y5, n_y4, n_y3, n_y2, n_y1, n_y0;
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`power wire vcc;
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wire [2:0] va;
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wire en;
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assign va = { a2, a1, a0 };
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assign en = ~n_e1 & ~n_e2 & e3;
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assign n_y0 = ~(en & (va == 0));
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assign n_y1 = ~(en & (va == 1));
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assign n_y2 = ~(en & (va == 2));
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assign n_y3 = ~(en & (va == 3));
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assign n_y4 = ~(en & (va == 4));
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assign n_y5 = ~(en & (va == 5));
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assign n_y6 = ~(en & (va == 6));
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assign n_y7 = ~(en & (va == 7));
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endmodule
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// F238: 3-to-8 line decoder/demultiplexer, active high.
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module f238(a0, a1, a2, n_e1, n_e2, e3, y7, gnd,
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y6, y5, y4, y3, y2, y1, y0, vcc);
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input wire a0, a1, a2, n_e1, n_e2, e3;
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output wire y7;
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`power wire gnd;
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output wire y6, y5, y4, y3, y2, y1, y0;
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`power wire vcc;
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wire [2:0] va;
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wire en;
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assign va = { a2, a1, a0 };
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assign en = ~n_e1 & ~n_e2 & e3;
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assign y0 = en & (va == 0);
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assign y1 = en & (va == 1);
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assign y2 = en & (va == 2);
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assign y3 = en & (va == 3);
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assign y4 = en & (va == 4);
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assign y5 = en & (va == 5);
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assign y6 = en & (va == 6);
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assign y7 = en & (va == 7);
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endmodule
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// F253: Dual 4-to-1 multiplexer.
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// Used for Macintosh Plus CPU/video/sound address selection.
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module f253(n_1g, b, s1c3, s1c2, s1c1, s1c0, s1y, gnd,
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s2y, s2c0, s2c1, s2c2, s2c3, a, n_2g, vcc);
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input wire n_1g, b, s1c3, s1c2, s1c1, s1c0;
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`output_wz wire s1y;
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`power wire gnd;
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`output_wz wire s2y;
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input wire s2c0, s2c1, s2c2, s2c3, a, n_2g;
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`power wire vcc;
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assign s1y = (n_1g) ? 'bz : sel1({ b, a });
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function sel1(input [1:0] selvec);
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case (selvec)
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0: sel1 = s1c0;
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1: sel1 = s1c1;
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2: sel1 = s1c2;
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3: sel1 = s1c3;
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endcase
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endfunction
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assign s2y = (n_2g) ? 'bz : sel2({ b, a });
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function sel2(input [1:0] selvec);
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case (selvec)
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0: sel2 = s2c0;
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1: sel2 = s2c1;
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2: sel2 = s2c2;
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3: sel2 = s2c3;
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endcase
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endfunction
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endmodule
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// F257: Quadruple 2-to-1 multiplexer. Used for RAS/CAS selection.
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// LS257: Logically the same as F257. (Only differs electrically.)
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module f257(n_a_b, s1a, s1b, s1y, s2a, s2b, s2y, gnd,
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s3y, s3b, s3a, s4y, s4b, s4a, n_oe, vcc);
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input wire n_a_b, s1a, s1b;
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`output_wz wire s1y;
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input wire s2a, s2b;
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`output_wz wire s2y;
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`power wire gnd;
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`output_wz wire s3y;
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input wire s3b, s3a;
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`output_wz wire s4y;
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input wire s4b, s4a, n_oe;
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`power wire vcc;
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assign s1y = (n_oe) ? 'bz : (~n_a_b) ? s1a : s1b;
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assign s2y = (n_oe) ? 'bz : (~n_a_b) ? s2a : s2b;
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assign s3y = (n_oe) ? 'bz : (~n_a_b) ? s3a : s3b;
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assign s4y = (n_oe) ? 'bz : (~n_a_b) ? s4a : s4b;
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endmodule
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// LS393: Dual 4-bit binary counter.
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// Used to generate sequential video and sound RAM addresses.
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module ls393(s1a, s1clr, s1q_a, s1q_b, s1q_c, s1q_d, gnd,
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s2q_d, s2q_c, s2q_b, s2q_a, s2clr, s2a, vcc);
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input wire s1a, s1clr;
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output wire s1q_a, s1q_b, s1q_c, s1q_d;
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`power wire gnd;
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output wire s2q_d, s2q_c, s2q_b, s2q_a;
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input wire s2clr, s2a;
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`power wire vcc;
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reg [3:0] s1reg;
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reg [3:0] s2reg;
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assign { s1q_d, s1q_c, s1q_b, s1q_a } = s1reg;
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assign { s2q_d, s2q_c, s2q_b, s2q_a } = s2reg;
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// N.B. These counters propagate the incremented value to the
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// output pins on the negative edge of the A input, unlike the '161
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// counter.
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// Also, for the sake of simulating the Macintosh 128K Main Logic
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// Board signals correctly, we must continuously evaluate the RESET
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// signals (not edge evaluate), due to the fact that we can have
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// glitches on the counter input while RESET is still being
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// held,and the fact that we need to assert the correct RESET value
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// early on.
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always @(s1clr)
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s1reg <= 0;
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always @(negedge s1a)
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s1reg <= s1reg + 1;
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always @(s2clr)
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s2reg <= 0;
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always @(negedge s2a)
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s2reg <= s2reg + 1;
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endmodule
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// LS595: 8-bit serial input, parallel output shift register, with
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// output latch.
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module ls595(q_b, q_c, q_d, q_e, q_f, q_g, q_h, gnd,
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q_h_p, n_srclr, srclk, rclk, n_oe, ser, q_a, vcc);
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output wire q_b, q_c, q_d, q_e, q_f, q_g, q_h;
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`power wire gnd;
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output wire q_h_p;
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input wire n_srclr, srclk, rclk, n_oe, ser;
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output wire q_a;
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`power wire vcc;
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reg [7:0] int_reg;
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reg [7:0] out_reg;
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assign { q_h, q_g, q_f, q_e, q_d, q_c, q_b, q_a }
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= (n_oe) ? 8'bz : int_reg;
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assign q_h_p = q_h;
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always @(negedge n_srclr) begin
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int_reg <= 0;
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end
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// N.B. As soon as the rising edge of the clock is detected under
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// the proper conditions, we propagate the shifted value to the
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// output pins. We do not wait until the next rising edge of the
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// clock.
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always @(posedge srclk) begin
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int_reg <= { int_reg[6:0], ser };
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end
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always @(posedge rclk) begin
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out_reg <= int_reg;
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end
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endmodule
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`endif // not STDLOGIC_V
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