Fix RTC

components/tme/emu.c

@@ -522,6 +522,10 @@ void tmeStartEmu(void *rom) {
 		frame++;
 		ca1^=1;
 		viaControlWrite(VIA_CA1, ca1);
+		if (frame==59) {
+			ca2^=1;
+			viaControlWrite(VIA_CA2, ca2);
+		}
 		if (frame>=60) {
 			ca2^=1;
 			viaControlWrite(VIA_CA2, ca2);

components/tme/m68kconf.h

@@ -74,6 +74,7 @@
  * If off, all read requests from the CPU will be redirected to m68k_read_xx()
  */
 #define M68K_SEPARATE_READS         OPT_ON
+//#define M68K_SEPARATE_READS         OPT_OFF
 
 
 /* If ON, the CPU will call m68k_write_32_pd() when it executes move.l with a

components/tme/rtc.c

@@ -1,6 +1,7 @@
 #include <stdint.h>
 #include <stdio.h>
 #include <string.h>
+#include <time.h>
 
 typedef struct {
 	int lastClkVal;
@@ -15,8 +16,9 @@ void rtcTick() {
 	int x;
 	for (x=0; x<3; x++) {
 		rtc.mem[x]++;
-		if (rtc.mem[x]!=0) return;
+		if (rtc.mem[x]!=0) break;
 	}
+	for (int i=0; i<4; i++) rtc.mem[i+4]=rtc.mem[i]; //undocumented; mac needs it tho'.
 }
 
 extern void saveRtcMem(char *mem);
@@ -36,12 +38,12 @@ int rtcCom(int en, int dat, int clk) {
 //			printf("RTC: clocktick %d, dataline %d, cmd %x\n", rtc.pos, dat, rtc.cmd);
 			if (rtc.cmd&0x8000) { //read
 				if (rtc.pos==8) {
-					printf("RTC: Read cmd %x\n", rtc.cmd>>8);
 					rtc.cmd|=rtc.mem[(rtc.cmd&0x7C00)>>10];
+//					printf("RTC: Read cmd %x val %x\n", rtc.cmd>>8, (rtc.cmd&0xff));
 				}
 				ret=((rtc.cmd&(1<<(15-rtc.pos)))?1:0);
 			} else if (rtc.pos==15) {
-				printf("RTC: Write cmd %x\n", rtc.cmd>>8);
+//				printf("RTC: Write cmd %x\n", rtc.cmd>>8);
 				rtc.mem[(rtc.cmd&0x7C00)>>10]=rtc.cmd&0xff;
 				saveRtcMem((char*)rtc.mem);
 			}

components/tme/scc.c

@@ -385,6 +385,7 @@ static void triggerRx(int chan) {
 void sccWrite(unsigned int addr, unsigned int val) {
 	int chan, reg;
 	if (addr & (1<<1)) chan=SCC_CHANA; else chan=SCC_CHANB;
+	if (scc.regptr>32) abort();
 	if (addr & (1<<2)) {
 		//Data
 		reg=8;
@@ -499,6 +500,9 @@ void sccWrite(unsigned int addr, unsigned int val) {
 unsigned int sccRead(unsigned int addr) {
 	int chan, reg, val=0xff;
 	if (addr & (1<<1)) chan=SCC_CHANA; else chan=SCC_CHANB;
+	if (scc.regptr>32) {
+		printf("WtF, regptr=%x?\n", scc.regptr);
+	}
 	if (addr & (1<<2)) {
 		//Data
 		reg=8;

components/tme/via.c

@@ -35,6 +35,7 @@ typedef struct {
 	uint8_t ifr, ier;
 	uint8_t pcr, acr;
 	uint8_t controlin[2];
+	int srTicks;
 } Via;
 
 static Via via;
@@ -53,21 +54,6 @@ void viaClear(int no, int mask) {
 	if (no==VIA_PORTA) via.ina&=~mask; else via.inb&=~mask;
 }
 
-void viaStep(int clockcycles) {
-	if ((via.timer1!=0) || (via.acr&(1<<6))) {
-		via.timer1-=clockcycles;
-		if (via.timer1<=1) {
-			via.ifr|=IFR_T1;
-			via.timer1+=via.latch1;
-		}
-	}
-	via.timer2-=clockcycles;
-	if (via.timer2<=0) {
-		//Actually shouldn't be set when timer2 gets 0 a 2nd time... ahwell.
-		via.ifr|=IFR_T2;
-		via.timer2+=0x10000;
-	}
-}
 
 static void viaCheckIrq() {
 	static int oldmint=0;
@@ -82,6 +68,38 @@ static void viaCheckIrq() {
 	}
 }
 
+void viaStep(int clockcycles) {
+	if ((via.timer1!=0) || (via.acr&(1<<6))) {
+		via.timer1-=clockcycles;
+		if (via.timer1<=1) {
+			via.ifr|=IFR_T1;
+			via.timer1+=via.latch1;
+		}
+	}
+	via.timer2-=clockcycles;
+	if (via.timer2<=0) {
+		//Actually shouldn't be set when timer2 gets 0 a 2nd time... ahwell.
+		via.ifr|=IFR_T2;
+		via.timer2+=0x10000;
+	}
+	if (via.srTicks) {
+		via.srTicks-=clockcycles;
+		if (via.srTicks<=0) {
+			via.ifr|=IFR_SR;
+			via.srTicks=0;
+		}
+	}
+
+	static int p=0;
+	p++;
+	if (p==200) {
+		p=0;
+		via.ifr|=0x4;
+	}
+
+	viaCheckIrq();
+}
+
 static int pcrFor(int no) {
 	const int shift[]={0, 1, 4, 5};
 	const int mask[]={1, 3, 1, 3};
@@ -93,12 +111,13 @@ static int pcrFor(int no) {
 	}
 }
 
+//Clears CB1/CA1 bits in IFR
 static void accessPort(int no) {
 	via.ifr&=~(no?IFR_CB1:IFR_CA1);
 	int pcrca2=pcrFor(no?VIA_CB2:VIA_CA2);
-	if (pcrca2==PCR_NEG || pcrca2==PCR_POS) {
+//	if (pcrca2==PCR_NEG || pcrca2==PCR_POS) {
 		via.ifr&=~(no?IFR_CB2:IFR_CA2);
-	}
+//	}
 	viaCheckIrq();
 }
 
@@ -161,6 +180,7 @@ void viaWrite(unsigned int addr, unsigned int val) {
 		viaCheckIrq();
 	} else if (addr==0xa) {
 		//SR
+		via.srTicks=8;
 //		printf("6522: Unimplemented: Write %x to SR?\n", val);
 	} else if (addr==0xb) {
 		//ACR
@@ -180,13 +200,17 @@ void viaWrite(unsigned int addr, unsigned int val) {
 			via.ier&=~val;
 		}
 		via.ier&=0x7f;
+		if (via.ier&0x18) {
+			printf("Unsupported int enabled. ier=%x\n", via.ier);
+			abort();
+		}
 		viaCheckIrq();
 	} else if (addr==0xf) {
 		//ORA
 		viaCbPortAWrite(val);
 		via.ina=(via.ina&~via.ddra)|(val&via.ddra);
 	}
-	printf("PC %x VIA write %s val %x\n", pc, viaRegNames[addr], val);
+//	printf("PC %x VIA write %s val %x\n", pc, viaRegNames[addr], val);
 }
 
 
@@ -231,6 +255,8 @@ unsigned int viaRead(unsigned int addr) {
 		val=via.timer2>>8;
 	} else if (addr==0xa) {
 		//SR
+		via.ifr&=~IFR_SR;
+		val=0xff;
 //		printf("6522: Unimplemented: Read from SR?\n");
 	} else if (addr==0xb) {
 		//ACR
@@ -248,6 +274,6 @@ unsigned int viaRead(unsigned int addr) {
 		//ORA
 		val=via.ina;
 	}
-	printf("PC %x VIA read %s val %x\n", pc, viaRegNames[addr], val);
+//	printf("PC %x VIA read %s val %x\n", pc, viaRegNames[addr], val);
 	return val;
 }