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added back panel using a PCB

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demik 2022-01-04 19:23:36 +01:00
parent f691dc34e6
commit 4ba1b4b113
5 changed files with 1150 additions and 0 deletions
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37
EDA/Panels/Back/quack_BP-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_TestPoint_Small
#
DEF Connector_TestPoint_Small TP 0 30 N N 1 F N
F0 "TP" 0 150 50 H V C CNN
F1 "Connector_TestPoint_Small" 0 80 50 H V C CNN
F2 "" 200 0 50 H I C CNN
F3 "" 200 0 50 H I C CNN
$FPLIST
Pin*
Test*
$ENDFPLIST
DRAW
C 0 0 20 0 1 0 N
X 1 1 0 0 0 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_Earth
#
DEF power_Earth #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_Earth" 0 -150 50 H I C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -25 -75 25 -75 N
P 2 0 1 0 -5 -100 5 -100 N
P 2 0 1 0 0 -50 0 0 N
P 2 0 1 0 50 -50 -50 -50 N
X Earth 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

110
EDA/Panels/Back/quack_BP-job.gbrjob Normal file
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{
"Header":
{
"GenerationSoftware":
{
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "(5.1.12-1-10_14)"
},
"CreationDate": "2021-12-08T14:43:14+01:00"
},
"GeneralSpecs":
{
"ProjectId":
{
"Name": "quack_BP",
"GUID": "71756163-6b5f-4425-902e-6b696361645f",
"Revision": "1.0"
},
"Size":
{
"X": 60.050,
"Y": 22.850
},
"LayerNumber": 2,
"BoardThickness": 1.600
},
"DesignRules":
[
{
"Layers": "Outer",
"PadToPad": 0.200,
"PadToTrack": 0.200,
"TrackToTrack": 0.200,
"MinLineWidth": 0.250,
"TrackToRegion": 0.508,
"RegionToRegion": 0.508
}
],
"FilesAttributes":
[
{
"Path": "quack_BP-F_Cu.gbr",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "quack_BP-B_Cu.gbr",
"FileFunction": "Copper,L2,Bot",
"FilePolarity": "Positive"
},
{
"Path": "quack_BP-F_SilkS.gbr",
"FileFunction": "Legend,Top",
"FilePolarity": "Positive"
},
{
"Path": "quack_BP-B_SilkS.gbr",
"FileFunction": "Legend,Bot",
"FilePolarity": "Positive"
},
{
"Path": "quack_BP-F_Mask.gbr",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "quack_BP-B_Mask.gbr",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "quack_BP-Edge_Cuts.gbr",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup":
[
{
"Type": "Legend",
"Notes": "Layer F.SilkS"
},
{
"Type": "SolderMask",
"Notes": "Layer F.Mask"
},
{
"Type": "Copper",
"Notes": "Layer F.Cu"
},
{
"Type": "Dielectric",
"Material": "FR4",
"Notes": "Layers L1/L2"
},
{
"Type": "Copper",
"Notes": "Layer B.Cu"
},
{
"Type": "SolderMask",
"Notes": "Layer B.Mask"
},
{
"Type": "Legend",
"Notes": "Layer B.SilkS"
}
]
}

701
EDA/Panels/Back/quack_BP.kicad_pcb Normal file
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(kicad_pcb (version 20171130) (host pcbnew "(5.1.12-1-10_14)")
(general
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(drawings 19)
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(page A4)
(title_block
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(date 2021-12-08)
(rev 1.0)
(company Lostwave)
(comment 1 https://68kmla.org)
(comment 2 https://github.com/quack/quack)
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(pcb_text_size 1.5 1.5)
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(module TestPoint:TestPoint_Pad_1.5x1.5mm (layer B.Cu) (tedit 5A0F774F) (tstamp 61B104B1)
(at 86 50.5)
(descr "SMD rectangular pad as test Point, square 1.5mm side length")
(tags "test point SMD pad rectangle square")
(path /61B0C87F)
(attr virtual)
(fp_text reference TP2 (at 0 1.648) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value TestPoint_Small (at 0 -1.75) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.95 0.95) (end 0.95 0.95) (layer B.SilkS) (width 0.12))
(fp_line (start 0.95 0.95) (end 0.95 -0.95) (layer B.SilkS) (width 0.12))
(fp_line (start 0.95 -0.95) (end -0.95 -0.95) (layer B.SilkS) (width 0.12))
(fp_line (start -0.95 -0.95) (end -0.95 0.95) (layer B.SilkS) (width 0.12))
(fp_line (start -1.25 1.25) (end 1.25 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.25 1.25) (end -1.25 -1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.25 -1.25) (end 1.25 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.25 -1.25) (end -1.25 -1.25) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 1.65) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 smd rect (at 0 0) (size 1.5 1.5) (layers B.Cu B.Mask)
(net 1 Earth))
)
(module TestPoint:TestPoint_Pad_1.5x1.5mm (layer B.Cu) (tedit 5A0F774F) (tstamp 61B10897)
(at 50.5 50.5)
(descr "SMD rectangular pad as test Point, square 1.5mm side length")
(tags "test point SMD pad rectangle square")
(path /61B0AF58)
(attr virtual)
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
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(fp_line (start 0.95 -0.95) (end -0.95 -0.95) (layer B.SilkS) (width 0.12))
(fp_line (start -0.95 -0.95) (end -0.95 0.95) (layer B.SilkS) (width 0.12))
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)
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(net 1 Earth))
)
(gr_text JLCJLCJLCJLC (at 68 59.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text "Use with Macintosh 128/512/Plus or Apple Lisa" (at 68 59.5) (layer F.SilkS)
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)
(gr_text Quack (at 46 50.5) (layer F.SilkS)
(effects (font (size 2 2) (thickness 0.3)))
)
(gr_arc (start 81.5 55) (end 81.5 57) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 61B100EF))
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248
EDA/Panels/Back/quack_BP.pro Normal file
View File

@ -0,0 +1,248 @@
update=2021 December 08, Wednesday 14:30:39
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
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MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
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TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
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CopperTextSizeV=1.5
CopperTextSizeH=1.5
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OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
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Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
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Enabled=0
[pcbnew/Layer.In10.Cu]
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Enabled=0
[pcbnew/Layer.In11.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
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Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=0
[pcbnew/Layer.F.Adhes]
Enabled=0
[pcbnew/Layer.B.Paste]
Enabled=0
[pcbnew/Layer.F.Paste]
Enabled=0
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=0
[pcbnew/Layer.Cmts.User]
Enabled=0
[pcbnew/Layer.Eco1.User]
Enabled=0
[pcbnew/Layer.Eco2.User]
Enabled=0
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

54
EDA/Panels/Back/quack_BP.sch Normal file
View File

@ -0,0 +1,54 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title "Quack back panel"
Date "2021-12-08"
Rev "1.0"
Comp "Lostwave"
Comment1 "https://68kmla.org"
Comment2 "https://github.com/quack/quack"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L power:Earth #PWR0101
U 1 1 61B0AB0B
P 3000 3000
F 0 "#PWR0101" H 3000 2750 50 0001 C CNN
F 1 "Earth" H 3000 2850 50 0001 C CNN
F 2 "" H 3000 3000 50 0001 C CNN
F 3 "~" H 3000 3000 50 0001 C CNN
1 3000 3000
1 0 0 -1
$EndComp
$Comp
L Connector:TestPoint_Small TP1
U 1 1 61B0AF58
P 3000 2500
F 0 "TP1" H 3048 2546 50 0000 L CNN
F 1 "TestPoint_Small" H 3048 2455 50 0000 L CNN
F 2 "TestPoint:TestPoint_Pad_1.5x1.5mm" H 3200 2500 50 0001 C CNN
F 3 "~" H 3200 2500 50 0001 C CNN
1 3000 2500
1 0 0 -1
$EndComp
Wire Wire Line
3000 3000 3000 2750
$Comp
L Connector:TestPoint_Small TP2
U 1 1 61B0C87F
P 3000 2750
F 0 "TP2" H 3048 2796 50 0000 L CNN
F 1 "TestPoint_Small" H 3048 2705 50 0000 L CNN
F 2 "TestPoint:TestPoint_Pad_1.5x1.5mm" H 3200 2750 50 0001 C CNN
F 3 "~" H 3200 2750 50 0001 C CNN
1 3000 2750
1 0 0 -1
$EndComp
Connection ~ 3000 2750
Wire Wire Line
3000 2750 3000 2500
$EndSCHEMATC