2004-02-15 20:46:45 +00:00
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/*
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*
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2006-09-15 14:55:39 +00:00
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* (c) 2004,2005 Laurent Vivier <Laurent@lvivier.info>
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2004-02-15 20:46:45 +00:00
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*
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*/
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2007-03-22 15:36:39 +00:00
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.cpu 68030
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2004-06-09 12:24:24 +00:00
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2004-06-09 17:34:40 +00:00
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.global MMU030_disable_cache
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MMU030_disable_cache:
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lea 0x0808, %a0
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2005-10-20 12:32:48 +00:00
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nop
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2004-06-09 17:34:40 +00:00
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movec %a0, %cacr
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rts
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2004-03-04 22:50:11 +00:00
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.global MMU030_get_TC
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MMU030_get_TC:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#0
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move.l 8(%fp),%a0
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pmove %tc,%a0@
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unlk %fp
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rts
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2004-03-04 22:50:11 +00:00
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.global MMU030_get_SRP
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MMU030_get_SRP:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#0
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move.l 8(%fp),%a0
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pmove %srp,%a0@
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unlk %fp
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rts
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2004-03-04 22:50:11 +00:00
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.global MMU030_get_CRP
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MMU030_get_CRP:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#0
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move.l 8(%fp),%a0
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pmove %crp,%a0@
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unlk %fp
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rts
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2004-03-04 22:50:11 +00:00
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.global MMU030_get_TT0
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MMU030_get_TT0:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#0
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move.l 8(%fp),%a0
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pmove %tt0, %a0@
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unlk %fp
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rts
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2004-03-04 22:50:11 +00:00
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.global MMU030_get_TT1
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MMU030_get_TT1:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#0
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move.l 8(%fp),%a0
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pmove %tt1,%a0@
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unlk %fp
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rts
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2004-03-04 22:50:11 +00:00
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.global MMU030_ptest
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MMU030_ptest:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#-8
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move.l 8(%fp),%a0
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/* test address */
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suba.l %a1, %a1
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ptestr #1,(%a0),#7,%a1
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/* get result */
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move.l 12(%fp),%a0
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move.l %a1,(%a0)
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lea -8(%fp),%a0
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pmove %psr,%a0@
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move.w %a0@, %d0
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unlk %fp
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rts
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.TT0: .long 0
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2004-03-04 22:50:11 +00:00
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.global MMU030_read_phys
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MMU030_read_phys:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#-8
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/* get the address to read */
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move.l 8(%fp),%d0
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move.l %d0,%a0
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/* save the %TT0 register */
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lea .TT0,%a1
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pmove %tt0,%a1@
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/* compute %TT0 new value */
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andi.l #0xFF000000, %d0 /* 8 high bits of address */
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ori.l #0x00008207, %d0 /* Enable, Caching allowed, read access
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* Ignore Function Code
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*/
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/* disable interrupts */
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move.l %d1,-(%sp)
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move %sr,%d1
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ori.w #0x0700,%sr
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/* set %TT0 with new value */
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move.l %d0, -8(%fp)
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pmove -8(%fp), %tt0
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/* read real memory */
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move.l %a0@,%d0
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/* restore %tt0 */
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pmove %a1@,%tt0
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/* restore interrupts */
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move %d1, %sr
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move.l (%sp)+, %d1
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unlk %fp
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rts
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2004-03-04 22:50:11 +00:00
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.global MMU030_write_phys
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MMU030_write_phys:
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2004-02-15 20:46:45 +00:00
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link.w %fp,#-8
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2005-06-01 23:26:24 +00:00
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move.l %d2,%sp@-
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2004-02-15 20:46:45 +00:00
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/* get the address to read */
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move.l 8(%fp),%d0
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move.l %d0,%a0
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move.l 12(%fp),%d2
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/* save the %TT0 register */
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lea .TT0,%a1
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pmove %tt0,%a1@
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/* compute %TT0 new value */
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andi.l #0xFF000000, %d0 /* 8 high bits of address */
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ori.l #0x00008007, %d0 /* Enable, Caching allowed, write access
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* Ignore Function Code
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*/
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/* disable interrupts */
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move.l %d1,-(%sp)
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move %sr,%d1
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ori.w #0x0700,%sr
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/* set %TT0 with new value */
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move.l %d0, -8(%fp)
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pmove -8(%fp), %tt0
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/* write real memory */
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move.l %d2, %a0@
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/* restore %tt0 */
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pmove %a1@,%tt0
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/* restore interrupts */
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move %d1, %sr
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move.l (%sp)+, %d1
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2005-06-01 23:26:24 +00:00
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move.l %sp@+, %d2
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2004-02-15 20:46:45 +00:00
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unlk %fp
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rts
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