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Add dynamic trace, TT registers management
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parent
9464758cf2
commit
610cf784a6
75
second/MMU.c
75
second/MMU.c
@ -62,12 +62,66 @@
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#define GET_TD_LF_NEXT(PD0, PD1) (PD1 & 0xFFFFFFFC)
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#define GET_TD_LF_ADDR(PD0, PD1) (PD1 & 0xFFFFFF00)
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#define GET_TT_ENABLE(TT) (TT & 0x0080)
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#define GET_TT_BASE(TT) ( (TT >> 24) & 0xFF )
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#define GET_TT_MASK(TT) ( (TT >> 16) & 0xFF )
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#ifdef TRACE_MMU
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#define TRACE(format, args...) printf(format, ##args)
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#define TRACE(format, args...) if (MMU_trace) printf(format, ##args)
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static int MMU_trace = 0;
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void MMU_set_trace(int enable)
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{
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MMU_trace = enable;
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}
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#else
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#define TRACE(format, args...)
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#endif
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static int isTTSegment(unsigned long addr)
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{
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unsigned long TT0;
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unsigned long TT1;
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unsigned long base;
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unsigned long mask;
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unsigned long size;
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addr >>= 24;
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get_TT0(&TT0);
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if (GET_TT_ENABLE(TT0))
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{
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mask = GET_TT_MASK(TT0);
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base = GET_TT_BASE(TT0);
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base &= ~mask;
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addr &= ~mask;
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size = (mask << 24) || 0x00FFFFFF;
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if ( (base <= addr) && (addr <= base + size) )
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return 1;
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}
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get_TT1(&TT1);
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if (GET_TT_ENABLE(TT1))
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{
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mask = GET_TT_MASK(TT1);
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base = GET_TT_BASE(TT1);
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base &= ~mask;
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addr &= ~mask;
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size = (mask << 24) || 0x00FFFFFF;
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if ( (base <= addr) && (addr <= base + size) )
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return 1;
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}
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/* if come here : no Transparent Translation */
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return 0;
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}
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static int decode_8_PD(unsigned long *pageBase, unsigned long *pageMask,
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unsigned long *attr,
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unsigned long logicalAddr, unsigned long TI,
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@ -82,7 +136,7 @@ static int decode_4_PD(unsigned long *pageBase, unsigned long *pageMask,
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unsigned long root;
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int index;
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TRACE("PD: %08lx\n", PD);
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TRACE("PD: %08lx ", PD);
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TIA = GET_TC_TIA(TI);
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@ -207,6 +261,19 @@ int logical2physicalAttr(unsigned long logicalAddr, unsigned long *physicalAddr,
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TRACE("logical: %08lx ", logicalAddr);
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*attr = 0;
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/* test if MMU is enabled */
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get_TC(&TC);
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TRACE("TC: %08lx\n", TC);
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if (!GET_TC_ENABLE(TC) || isTTSegment(logicalAddr))
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{
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*physicalAddr = logicalAddr;
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return 0;
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}
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/* analyse CPU root pointer */
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get_CRP(CRP);
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@ -218,9 +285,6 @@ int logical2physicalAttr(unsigned long logicalAddr, unsigned long *physicalAddr,
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/* analyse translation control register */
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get_TC(&TC);
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TRACE("TC: %08lx\n", TC);
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TIA = GET_TC_TIA(TC);
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is = GET_TC_IS(TC);
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@ -233,7 +297,6 @@ int logical2physicalAttr(unsigned long logicalAddr, unsigned long *physicalAddr,
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root = GET_RP_ADDR(CRP);
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*attr = 0;
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switch(dt)
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{
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case DT_INVALID:
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