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https://github.com/vivier/EMILE.git
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76 lines
2.0 KiB
OpenEdge ABL
76 lines
2.0 KiB
OpenEdge ABL
.equ MSR_LG_EE, 0 # Little Endian
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.equ MSR_LG_RI, 1 # Exception
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.equ MSR_LG_PMM, 2 # Performance monitor
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.equ MSR_LG_PX, 2 # Protection Exclusive Mode
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.equ MSR_LG_PE, 3 # Protection Enable
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.equ MSR_LG_DR, 4 # Data Relocate
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.equ MSR_LG_IR, 5 # Instruction Relocate
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.equ MSR_LG_IP, 6 # Exception prefix 0x000/0xFFF
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.equ MSR_LG_FE1, 8 # Floating Exception mode 1
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.equ MSR_LG_DE, 9 # Debug Exception Enable
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.equ MSR_LG_BE, 9 # Branch Trace
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.equ MSR_LG_SE, 10 # Single Step
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.equ MSR_LG_FE0, 11 # Floating Exception mode 0
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.equ MSR_LG_ME, 12 # Machine Check Enable
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.equ MSR_LG_FP, 13 # Floating Point enable
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.equ MSR_LG_PR, 14 # Problem State / Privilege Level
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.equ MSR_LG_EE, 15 # External Interrupt Enable
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.equ MSR_LG_ILE, 16 # Interrupt Little Endian
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.equ MSR_LG_CE, 17 # Critical Interrupt Enable
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.equ MSR_LG_TGPR, 17 # TLB Update registers in use
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.equ MSR_LG_WE, 18 # Wait State Enable
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.equ MSR_LG_POW, 18 # Enable Power Management
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.equ MSR_LG_VEC, 25 # Enable AltiVec
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.equ MSR_LG_HV, 60 # Hypervisor state
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.equ MSR_LG_ISF, 61 # Interrupt 64b mode valid on 630
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.equ MSR_LG_SF, 63 # Enable 64 bit mode
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.macro MSR name
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.equ MSR_\name, 1<<MSR_LG_\name
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.endm
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MSR EE
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MSR ME
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MSR IR
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MSR DR
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.irp reg,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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.equ r\reg, \reg
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.endr
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.equ DBAT0L, 0x219
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.equ DBAT0U, 0x218
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.equ DBAT1L, 0x21B
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.equ DBAT1U, 0x21A
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.equ DBAT2L, 0x21D
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.equ DBAT2U, 0x21C
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.equ DBAT3L, 0x21F
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.equ DBAT3U, 0x21E
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.equ DBAT4L, 0x239
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.equ DBAT4U, 0x238
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.equ DBAT5L, 0x23B
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.equ DBAT5U, 0x23A
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.equ DBAT6L, 0x23D
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.equ DBAT6U, 0x23C
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.equ DBAT7L, 0x23F
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.equ DBAT7U, 0x23E
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.equ IBAT0L, 0x211
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.equ IBAT0U, 0x210
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.equ IBAT1L, 0x213
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.equ IBAT1U, 0x212
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.equ IBAT2L, 0x215
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.equ IBAT2U, 0x214
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.equ IBAT3L, 0x217
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.equ IBAT3U, 0x216
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.equ IBAT4L, 0x231
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.equ IBAT4U, 0x230
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.equ IBAT5L, 0x233
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.equ IBAT5U, 0x232
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.equ IBAT6L, 0x235
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.equ IBAT6U, 0x234
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.equ IBAT7L, 0x237
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.equ IBAT7U, 0x236
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.equ PVR, 0x11F /* Processor Version Register */
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