270 lines
9.5 KiB
C
270 lines
9.5 KiB
C
/* cpu.h x86 cpu-description header-file */
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/* (c) in 2005-2006,2017 by Frank Wille */
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#define LITTLEENDIAN 1
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#define BIGENDIAN 0
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#define VASM_CPU_X86 1
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#define MNEMOHTABSIZE 0x8000
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/* maximum number of operands in one mnemonic */
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#define MAX_OPERANDS 3
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/* maximum number of mnemonic-qualifiers per mnemonic */
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#define MAX_QUALIFIERS 1
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/* data type to represent a target-address */
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typedef int64_t taddr;
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typedef uint64_t utaddr;
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/* minimum instruction alignment */
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#define INST_ALIGN 1
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/* default alignment for n-bit data */
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#define DATA_ALIGN(n) 1
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/* default alignment mode for .align directive */
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#define CPU_DEF_ALIGN 1 /* alignment in bytes */
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/* operand class for n-bit data definitions */
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int x86_data_operand(int);
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#define DATA_OPERAND(n) x86_data_operand(n)
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/* make sure operand is cleared upon first entry into parse_operand() */
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#define NEED_CLEARED_OPERANDS 1
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/* register symbols */
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#define HAVE_REGSYMS
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#define REGSYMHTSIZE 64
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/* reg_flags: */
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#define RegRex 0x1 /* Extended register. */
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#define RegRex64 0x2 /* Extended 8 bit register. */
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/* type to store each operand */
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typedef struct {
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int type; /* real type of operand */
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int parsed_type; /* type recognized by parser */
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unsigned int flags;
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expr *value; /* displacement or immediate value */
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regsym *basereg; /* base-reg. for SIB or single register */
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regsym *indexreg;
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expr *scalefactor;
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regsym *segoverride;
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int log2_scale; /* 0-3 for scale factor 1,2,4,8 */
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} operand;
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/* register operand types */
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#define Reg8 0x1
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#define Reg16 0x2
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#define Reg32 0x4
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#define Reg64 0x8
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/* immediate operand types*/
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#define Imm8 0x10
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#define Imm8S 0x20
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#define Imm16 0x40
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#define Imm32 0x80
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#define Imm32S 0x100
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#define Imm64 0x200
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#define Imm1 0x400 /* for 1-bit shift-instructions */
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/* memory operand types */
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#define Disp8 0x800
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#define Disp16 0x1000
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#define Disp32 0x2000
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#define Disp32S 0x4000
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#define Disp64 0x8000
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#define BaseIndex 0x10000 /* indirect base-register has optional index */
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/* special operand types */
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#define ShiftCntReg 0x20000 /* Shift-count register (%cl) */
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#define IOPortReg 0x40000 /* I/O port register (%dx) */
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#define CtrlReg 0x80000
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#define DebugReg 0x100000
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#define TestReg 0x200000
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#define Acc 0x400000 /* Accumulator (%al or %ax or %eax) */
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#define SegReg2 0x800000 /* Segment register with 2 bits */
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#define SegReg3 0x1000000 /* Segment register with 3 bits */
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#define MMXReg 0x2000000
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#define XMMReg 0x4000000
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#define FloatReg 0x8000000 /* Float register %st(n) */
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#define FloatAcc 0x10000000 /* Float stack top %st(0), float-accumulator */
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#define EsSeg 0x20000000 /* String instr. oper. with fixed ES seg. */
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#define JmpAbs 0x40000000 /* Absolute jump/call instruction */
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#define InvMem 0x80000000 /* modrm-byte doesn't support memory form */
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/* data operands (@@@ define their own flags?) */
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#define FloatData (FloatAcc)
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#define Data8 (Disp8)
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#define Data16 (Disp16)
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#define Data32 (Disp32)
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#define Data64 (Disp64)
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#define Float32 (Disp32|FloatData)
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#define Float64 (Disp64|FloatData)
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/* operand type groups */
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#define Reg (Reg8|Reg16|Reg32|Reg64)
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#define WordReg (Reg16|Reg32|Reg64)
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#define AnyReg (Reg|MMXReg|XMMReg|SegReg2|SegReg3|CtrlReg|DebugReg|TestReg)
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#define ImpliedReg (IOPortReg|ShiftCntReg|Acc|FloatAcc)
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#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64)
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#define EncImm (Imm8|Imm16|Imm32|Imm32S)
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#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64)
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#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)
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/* currently we do not differentiate between those memory types, */
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/* but the opcode table is prepared for it */
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#define LLongMem AnyMem
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#define LongMem AnyMem
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#define ShortMem AnyMem
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#define WordMem AnyMem
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#define ByteMem AnyMem
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/* flags */
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#define OPER_REG 1 /* operand is a direct register */
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#define OPER_PCREL 2 /* PC-relative operand */
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/* x86 opcode prefixes */
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#define WAIT_PREFIX 0
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#define LOCKREP_PREFIX 1
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#define ADDR_PREFIX 2
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#define DATA_PREFIX 3
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#define SEG_PREFIX 4
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#define REX_PREFIX 5 /* must be the last one */
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#define MAX_PREFIXES 6 /* maximum number of prefixes */
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/* x86 segment register numbers */
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#define ESEG_REGNUM 0
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#define CSEG_REGNUM 1
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#define SSEG_REGNUM 2
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#define DSEG_REGNUM 3
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#define FSEG_REGNUM 4
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#define GSEG_REGNUM 5
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/* Mod-R/M byte, which follows the opcode */
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typedef struct {
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unsigned char mode; /* how to interpret regmem & reg */
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unsigned char reg; /* register operand or extended opcode */
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unsigned char regmem; /* register or memory operand (addr.mode) */
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} modrm_byte;
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/* SIB (scale, index, base) byte, which follows modrm_byte in some
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i386 addressing modes */
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typedef struct {
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unsigned char scale; /* scale-factor (1, 2, 4 or 8) */
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unsigned char index; /* index register */
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unsigned char base; /* base register */
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} sib_byte;
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#define EBP_REGNUM 5
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#define ESP_REGNUM 4
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/* modrm_byte.regmem for 2-byte opcode escape */
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#define TWO_BYTE_ESCAPE (ESP_REGNUM)
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/* sib_byte.index for no index register */
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#define NO_INDEXREG (ESP_REGNUM)
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/* sib_byte.base for no base register */
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#define NO_BASEREG (EBP_REGNUM)
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#define NO_BASEREG16 6
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/* instruction extension */
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#define HAVE_INSTRUCTION_EXTENSION 1
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typedef struct {
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uint32_t base_opcode;
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unsigned char flags;
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unsigned char num_prefixes;
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unsigned char prefix[MAX_PREFIXES];
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modrm_byte rm;
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sib_byte sib;
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short last_size;
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} instruction_ext;
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/* flags: */
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#define HAS_REG_OPER 0x1 /* inst. has direct-register operands */
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#define SUFFIX_CHECKED 0x2 /* suffix assigned and checked */
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#define MODRM_BYTE 0x4 /* needs mod/rm byte */
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#define SIB_BYTE 0x8 /* needs sib byte */
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#define NEGOPT 0x40 /* negatively optimized, bytes gained */
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#define POSOPT 0x80 /* positively optimized, bytes gained */
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#define OPTFAILED (POSOPT|NEGOPT) /* no longer try to optimize this */
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/* max_opt_tries:
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An instruction optimized more frequent than that is been considered
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'oscillating' (e.g. by effects of alignment-directives) and should
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no longer be optimized! */
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#define MAX_OPT_TRIES 10
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/* additional mnemonic data */
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typedef struct {
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uint32_t base_opcode;
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uint32_t extension_opcode;
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uint32_t opcode_modifier;
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uint32_t available;
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} mnemonic_extension;
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/* extension_opcode */
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#define NO_EXTOPCODE 0xffff
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/* cpu available flags: */
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#define CPU086 0x1
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#define CPU186 0x2
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#define CPU286 0x4
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#define CPU386 0x8
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#define CPU486 0x10
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#define CPU586 0x20
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#define CPU686 0x40
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#define CPUP4 0x80
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#define CPUK6 0x100
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#define CPUAthlon 0x200
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#define CPUSledgehammer 0x400
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#define CPUMMX 0x800
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#define CPUSSE 0x1000
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#define CPUSSE2 0x2000
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#define CPU3dnow 0x4000
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#define CPUPNI 0x8000
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#define CPUPadLock 0x10000
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#define CPU64 0x4000000
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#define CPUNo64 0x8000000
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#define CPUAny (CPU086|CPU186|CPU286|CPU386|CPU486|CPU586|CPU686|CPUP4|CPUSledgehammer|CPUMMX|CPUSSE|CPUSSE2|CPUPNI|CPU3dnow|CPUK6|CPUAthlon|CPUPadLock)
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/* opcode_modifier: */
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#define W 0x1 /* operands can be words or dwords */
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#define M 0x4 /* has Modrm byte */
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#define FloatR 0x8 /* swapped src/dest for floats: MUST BE 0x8 */
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#define ShortForm 0x10 /* reg. enc. in 3 low-order bits of opcode */
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#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
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#define Jmp 0x40 /* relative conditional and uncond. branches */
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#define JmpDword 0x80 /* relative 16/32 bit calls */
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#define JmpByte 0x100 /* loop and jecxz */
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#define JmpInterSeg 0x200 /* inter segment calls and branches */
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#define FloatD 0x400 /* direction for FP insns: MUST BE 0x400 */
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#define Seg2ShortForm 0x800 /* 2-bit segment reg. encoded in opcode */
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#define Seg3ShortForm 0x1000 /* 3-bit segment reg. encoded in opcode */
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#define Size16 0x2000 /* needs a size prefix in 32-bit mode */
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#define Size32 0x4000 /* needs a size prefix in 16-bit mode */
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#define Size64 0x8000 /* needs a size prefix in 16-bit mode */
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#define IgnoreSize 0x10000 /* operand size prefix is ignored */
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#define DefaultSize 0x20000 /* default instruction size depends on mode */
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#define b_Illegal 0x40000 /* b suffix is illegal */
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#define w_Illegal 0x80000 /* w suffix is illegal */
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#define l_Illegal 0x100000 /* l suffix is illegal */
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#define s_Illegal 0x200000 /* s suffix is illegal */
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#define q_Illegal 0x400000 /* q suffix is illegal */
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#define x_Illegal 0x800000 /* x suffix is illegal */
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#define FWait 0x1000000 /* needs an FWAIT prefix */
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#define StrInst 0x2000000 /* string instructions */
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#define FakeLastReg 0x4000000 /* duplicate last reg. for clr and imul */
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#define IsPrefix 0x8000000 /* opcode is a prefix */
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#define ImmExt 0x10000000 /* has extension in 8 bit immediate */
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#define NoRex64 0x20000000 /* doesn't require REX64 prefix */
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#define Rex64 0x40000000 /* requires REX64 prefix */
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#define Deprecated 0x80000000 /* deprecated FPU instruction */
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