# KE8-E Extended Arithmetic Element

The instructions for the KE8-E Extended Arithmetic Element are operate instructions with bits 3 and 11 set. They are microprogrammable and are often called Group 3 Microoperations.

With the PDP-8/E (not with earlier models), the EAE has two operation modes. In mode A, the EAE is software compatible to older PDP-8 EAEs; in mode B, it provides an extended set of instructions. The PDP-8/E (not the earlier models PDP-8, -8/S, -8/I, -8/L) has the MQ register and the group 3 microoperations NOP (7401), MQL (7421), MQA (7501), and CLA (7601) (and their microprogrammed combinations, e. g. SWP (7521), CAM (7621), ACL (7701)) even if it has no EAE.

Some of the EAE instructions require a direct operand in an extension word of the instruction. Some mode B instructions use this extension word for indirect addressing of the operand. In this case, when the extension word is located in an autoindexing memory location (0010–0017 on each field), autoincrementing takes place, i. e. the extension word is incremented before it is used as the operands address.

Bit assignments of the group 3 microinstructions:

Mode A:

SCA

Bits 8–10
0 - NOP | 4 - NMI
1 - SCL | 5 - SHL
2 - MUY | 6 - ASR
3 - DVI | 7 - LSR

Mode A and B: |  | CLA | MQA |  | MQL |  |
| Opcode 111 |  | 1
Bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11

Mode B:

Group Bit: 1
(with Bit 11 = 1):
Group 3

Bits 6 and 8–10
00 - NOP | 10 - SCA
01 - ACS | 11 - DAD
02 - MUY | 12 - DST
03 - DVI | 13 - SWBA
04 - NMI | 14 - DPSZ
05 - SHL | 15 - DPIC
06 - ASR | 16 - DCM
07 - LSR | 17 - SAM

Mnemonic Symbol | Octal Code | Sequence/ EAE Mode | Description
--- | --- | --- | ---
NOP | 7401 | −/A,B | No operation.
CLA | 7601 | 1/A,B | Clear AC. The AC is cleared during sequence 1, allowing this command to be combined with EAE commands that load AC during sequence 2.
MQA | 7501 | 2/A,B | Load MQ into AC (by performing a logical OR of AC and MQ).
MQL | 7421 | 2/A,B | Load MQ from AC, then clear AC.
SWP | 7521 | 2/A,B | Swap the contents of AC and MQ. Microprogrammed combination of MQA and MQL.
ACL | 7701 | 1,2/A,B | Load MQ into AC. Microprogrammed combination of CLA and MQA.
CAM | 7621 | 1,2/A,B | Clear AC and MQ. Microprogrammed combination of CLA and MQL.
SWAB | 7431 | 2/A,B | Switch to EAE mode B (and execute MQL).
SCA # | 7403 | 3/A | Load SC from memory. Loads the complement of bis 7–11 of the memory word following the instruction into the step counter.
ACS | 7403 | 3/B | Load SC from AC(7–11) and then clear AC.
MUY # | 7405 | 3/A | Multiply. The number held in MQ is multiplied by the number held in the memory word following the instruction. The most significatn 12 bits of the product are containted in AC and the least significatn 12 bits are contained in MQ.

DVI #

7407

3/A

Divide. The 24-bit dividend held in AC (most significant 12 bits) and MQ (least significant 12 bits) is divided by the number held in the memory word following the instruction. After execution of this instruction the quotient is held in MQ, the remainder is held in AC, and L is cleared. If L contains a one, a divide overflow occured and the operation was aborted after the first cycle of the division.

DVI # | 7407 | 3/B | Same as mode A divide, but the word following the instruction does not contain the divisor, but the address (in DF) of the divisor.

NMI

7411

3/A,B

Normalize. This instruction is used as part of the conversion of a binary number to a fraction and an exponent for use in floating point arithmetic. The combined content of AC and MQ is shifted left by this command until AC(0) ≠ AC(1) (or AC(2–11) and MQ become zero). Zeros are shifted into the vacated MQ(11) positions. At the conclusion of this operation, the step counter SC contains the number of shifts performed. The content of L is lost. (In mode B operation, if, at the end of the normalization, only AC(0) is set (and AC(1–11) and MQ are zero), then AC is cleared.) NMI nust not be combined with other EAE operations.

SHL # | 7413 | 3/A,B | Shift arithmetic left. This instruction shifts the combined content of AC and MQ to the left one more than the number of positions (mode A) resp. exactly the number of positions (mode B) indicated by the content of the memory location following the instruction. During the shifting, zeros are shifted into vacated MQ(11) positions.

ASR #

7415

3/A,B

Arithmetic shift right. The combined content of AC and MQ is shifted right one position more than (mode A) resp. exactly the number of positions (mode B) contained in the memory location following the instruction. The sign bit, contained in AC(0), enters vacated positions. In mode B operation, GTF receives the last digit shifted out of MQ(11). SC is set to zero in mode A and to 37 (octal) in mode B operation.

LSR # | 7417 | 3/A,B | Logical shift right. This instruction works as ASR except that zeros enter vacated positions at AC(0) instead of the sign bit.

DAD #

7443

3/B

Double word addition. The content of the memory word following the instruction is used as the address (in DF) of a double word in memory (first word: least significant 12 bits, second word: most significant 12 bits.) This double word is added to the 24-bit number contained in AC (most significant 12 bits) and MQ (least significant 12 bits). The result is stored in AC and MQ; L receives the carry.

SWBA | 7447 | 3/A,B | Switch to EAE mode A (and clear GTF). When it is combined with other EAE operations, SWBA is ignored when running in EAE mode B.
DPSZ | 7451 | 3/B | Skip the next instruction if the double word held in AC and MQ is zero.
DPIC | 7573 | 3/B | Increment the double word held in AC and MQ by one. If an overflow occurs, L receives the carry. (The DPIC instruction requires the MQA and MQL bits to be set. If they are not set (opcode 7453), the increment takes place for the double word with MSBs in MQ and LSBs in AC.)
DCM | 7575 | 3/B | Build the two’s complement of the double word held in AC and MQ. If an overflow occurs, L receives the carry. (The DCM instruction requires the MQA and MQL bits to be set. If they are not set (opcode 7455), the complement is build for the double word with MSBs in MQ and LSBs in AC.)
SAM | 7457 | 3/B | Subtract. The content of AC is subtracted form the content of MQ, and the result is stored in AC. The values in AC and MQ are treated as signed two’s complement numbers. The greater than flag GTF is set to one if the result of the subtraction is positiv, otherwise it is cleared.
DLD # | 7663 | 1–3/B | Load double word. This is the microprogrammed combination of CLA, MQL and DAD.
DDZ # | 7665 | 1–3/B | Store double word zero in memory. This is the microprogrammed combination of CLA, MQL and DST.
SGT | 6006 | −/B | Skip on GTF. The next instruction is skipped if the greater than flag is set. Note that this is an IOT instruction.