# Operate Instructions

The operate instructions allow a program to manipulate or test the data located in AC and the L flag. Many different instructions are possible with one operation code because the operand bits are not needed to specify an address as they are in a MRI and can be used to specify different instructions. Combining more than one operation in an OPR instruction by setting more than one operation bit is called Microprogramming. The instructions that can be combined in one OPR — called Microoperations — are executed in a defined order: they have a Sequence Number between one and four, and they are executed in the order of their sequence numbers. The operate instructions are separated in two groups: Group 1, which contains manipulation instructions, and Group 2, which is primarily concerned with testing operations.

## Group 1 Microinstructions

Bit assignments of the group 1 microinstructions:

| Opcode 111 |  | CLA | CLL | CMA | CML | RAR | RAL |  | IAC
Bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11
| Group Bit: 0: Group 1 1: Group 2 |  | BSW or Rotate Count: 0: Rotate once 1: Rotate twice

Mnemonic | Seq. | Description
--- | --- | ---
CLA | 1 | Clear the accumulator. If bit 4 is one, the instruction sets the accumulator to all zeros.
CLL | 1 | Clear the link flag. If bit 5 is one, the link flag is set to zero.
CMA | 2 | Complement the accumulator. If bit 6 is one, the accumulator is set to the one’s complement of its original value.
CML | 2 | Complement the link flag. If bit 7 is one, the state of the link flag is reversed by the instruction.
RAR | 4 | Rotate the accumulator and the link flag right. If bit 8 is one and bit 10 is zero, the instruction treats AC and L as a closed loop and shifts all bits in the loop one position to the right.
RTR | 4 | Rotate the accumulator and the link flag twice right. If bit 8 is one and bit 10 is also one, a circular shift of two places to the right is executed.
RAL | 4 | Rotate the accumulator and the link flag left. If bit 9 is one and bit 10 is zero, the instruction treats AC and L as a closed loop and shifts all bits in the loop one position to the left.
RTL | 4 | Rotate the accumulator and the link flag twice left. If bit 9 is one and bit 10 is also one, a circular shift of two places to the left is executed.
BSW | 4 | Swap the bytes in the accumulator. If bit 10 is one and bits 8 and 9 are zero, the instruction swaps the two 6-bit bytes in AC(0–5) and AC(6–11).
IAC | 3 | Increment the accumulator. When bit 11 is one, the content of AC is incremented by one.
NOP | − | No operation. If bits 4 through 11 contain zeros, no operation is performed and program control is transferred to the next instruction of the program.

### Remarks

- The byte swap operation BSW is not available on earlier PDP-8 models (PDP-8, PDP-8/S, PDP-8/I, PDP-8/L).
- The combination of IAC with rotate microoperations is not allowed on the original PDP-8 and the PDP-8/S.
- The combination of CMA with rotate microoperations is not allowed on the PDP-8/S.
- The meaningless combination of the RAR and RAL microoperation have special effects on the different PDP-8 models which allow a program to determine the model it is running on. On the original PDP-8, combinations of RAR and RAL or RTR and RTL have unpredictable results. On the PDP-8/I and PDP-8/L, they produce the logical AND of the expected results from each of the combined shifts. On the PDP-8/E, /F, and /M, the combination of RAR and RAL produces the logical AND of AC with the opcode, and the combination of RTR and RTL does an effective address computation loading the five high bits of AC with the current page and the lower bits of AC with lower seven bits (page address) of the OPR instruction. On the PDP-8/A, combination of RAR and RAL produces the logical AND of AC with the opcode, and the combination of RTR and RTL loads the next address into AC. In the CPU window, OPR instructions with RAR and RAL combinations are disassembled as “(reserved)”.

## Group 2 Microinstructions

Bit assignments of the group 2 microinstructions:

| Opcode 111 |  | CLA | SMA SPA | SZA SNA | SNL SZL |  | OSR | HLT | 0
Bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11
| Group Bit: 0: Group 1 1: Group 2 |  | Reverse Sensing Bit: 0: SMA, SZA, SNL 1: SPA, SNA, SZL

Mnemonic | Seq. | Description
--- | --- | ---
CLA | 2 | Clear the accumulator. If bit 4 is one, the instruction sets the accumulator to all zeros.
SMA | 1 | Skip on minus accumulator. If bit 5 is one and bit 8 is zero, the next instruction is skipped if the accumulator is less than zero.
SPA | 1 | Skip on positive accumulator. If bit 5 is one and bit 8 is also one, the next instruction is skipped if the accumulator is greater than or equal to zero.
SZA | 1 | Skip on zero accumulator. If bit 6 is one and bit 8 is zero, the next instruction is skipped if the accumulator is zero.
SNA | 1 | Skip on nonzero accumulator. If bit 6 is one and bit 8 is also one, the next instruction is skipped if the accumulator is not zero.
SNL | 1 | Skip on nonzero link. If bit 7 is one and bit 8 is zero, the next instruction is skipped when the link flag is one.
SZL | 1 | Skip on zero link. If bit 7 is one and bit 8 is also one, the next instruction is skipped when the link flag is zero.
SKP | 1 | Unconditional skip. If bit 8 is one and bits 5 to 7 are all zeros, the next instruction is skipped.
OSR | 3 | Logical OR of the switch register and AC. If bit 9 is one, a logical OR operation is performed between the content of the accumulator and the console switch register SR. The result is left in AC.
HLT | 3 | Halt. If bit 10 is one, the computer will stop at the conclusion of the current machine cycle.
NOP | − | No operation. If bits 4 through 11 contain zeros, no operation is performed and the program control is transferred to the next instruction of the program.

### Remarks

- When SMA, SZA or SNL are combined (bit 8 of the instruction is zero), the skip takes place if one of the conditions is true, i. e. when the logical OR of the results of the condition tests is true. When SPA, SNA or SZL are combined (bit 8 of the instruction is one), the skip takes place if all conditions simultaneously are true, i. e. when the logical AND of the results of the condition tests is true.
- For Group 2 OPRs, bit 11 is always zero. When the group bit 3 and bit 11 of an OPR instruction are one, it is an instruction for the Extended Arithmetic Element. EAE microoperations are also called Group 3 microoperations.

## Mnemonics for OPR instructions

Some usefull microoperation combinations have special mnemonics recognized by PDP-8 assemblers. They and the basic OPR instructions are listed in the following table. Note that the CPU window disassembles combined microoperations as a sequence of basic microoperations in the order of their sequence numbers, i. e. execution order.

Mnemonic | Octal | Seq. | Description
--- | --- | --- | ---
NOP | 7000 | − | No operation. | Group 1
IAC | 7001 | 3 | Increment AC.
RAL | 7004 | 4 | Rotate AC and L circular left.
RTL | 7006 | 4 | Rotate AC and L twice circular left.
RAR | 7010 | 4 | Rotate AC and L curcular right.
RTR | 7012 | 4 | Rotate AC and L twice circular right.
CML | 7020 | 2 | Complement L.
CMA | 7040 | 2 | Complement AC.
CIA | 7041 | 2,3 | Complement and increment AC, i. e. built the two’s complement of AC.
CLL | 7100 | 1 | Clear L.
CLL RAL | 7104 | 1,4 | Shift positive number one left.
CLL RTL | 7106 | 1,4 | Clear L, rotate two left.
CLL RAR | 7110 | 1,4 | Shift positive number one right.
CLL RTR | 7112 | 1,4 | Clear L, rotate two right.
STL | 7120 | 1,2 | Set L = 1.
CLA | 7200 | 1 | Clear AC.
CLA IAC | 7201 | 1,3 | Set AC = 1.
GLK | 7204 | 1,4 | Get link. Transfer L into AC(11).
CLA CLL | 7300 | 1 | Clear AC and L.
STA | 7240 | 2 | Set AC = −1.
BSW | 7002 | 4 | Byte swap of AC(0–5) and AC(6–11). |
HLT | 7402 | 3 | Halt the computer. | Group 2
OSR | 7404 | 3 | Logical OR AC with SR.
SKP | 7410 | 1 | Skip unconditionally.
SNL | 7420 | 1 | Skip if L ≠ 0.
SZL | 7430 | 1 | Skip if L = 0.
SZA | 7440 | 1 | Skip if AC = 0.
SNA | 7450 | 1 | Skip if AC ≠ 0.
SZA SNL | 7460 | 1 | Skip if AC = 0 or L = 1.
SNA SZL | 7470 | 1 | Skip if AC ≠ 0 and L = 0.
SMA | 7500 | 1 | Skip if AC < 0.
SPA | 7510 | 1 | Skip if AC ≥ 0.
SMA SNL | 7520 | 1 | Skip if AC < 0 or L = 1.
SPA SZL | 7530 | 1 | Skip if AC ≥ 0 and L = 0.
SMA SZA | 7540 | 1 | Skip if AC ≤ 0.
SPA SNA | 7550 | 1 | Skip if AC > 0.
CLA | 7600 | 2 | Clear AC.
LAS | 7604 | 2,3 | Load AC with SR.
SZA CLA | 7640 | 1,2 | Skip if AC = 0, then clear AC.
SNA CLA | 7650 | 1,2 | Skip if AC ≠ 0, then clear AC.
SMA CLA | 7700 | 1,2 | Skip if AC < 0, then clear AC.
SPA CLA | 7710 | 1,2 | Skip if AC ≥ 0, then clear AC.