Controls and Indicators of the KC8-EA Programmer’s Console

The controls and indicators on the Programmer’s Console provide manual control and indicate the program conditions of the PDP-8/E. Controls on the Programmer’s Console provide the operator with the hardware to start, stop, examine, modify, or continue a program. The indicators on the console provide a visual indication of the machine status and current program, the contents of the major registers, and the condition of the control flip-flops. A lighted indicator denotes the presence of a binary 1 in a specific register bit position or control flip-flop. The table below lists the functions of controls and indicators. The controls are divided into two groups; switches and keys. Keys are momentary, or spring-return, switches.

Control or Indicator

Function

Off / Power / Panel Lock

This is a key operated switch. In the counter-clockwise, or OFF, position, the switch disconnects all primary power to the machiine. In the POWER, or straight up position, it enables all manual controls and applies primary computer power. In the PANEL LOCK or clockwise position, it disables all keys and switches with the exception of the Switch Register and the SW switch. In this position, a running program is protected from inadvertent switch operation and all panel indicators except the RUN light are turned off.

When this switch is up, the line on the OMNIBUS called SW is high; when the lever is down, the line is low. This switch is used by special peripheral controls, such as the Bootstrap Loader.

Switch Register Switches
(SR)

These 12 switches provide a means of communication between operator and machine. They allow a 12-bit word to be input. When the switch is up, it designates a binary 1 to the machine; switch down is a 0. These switches are used during manual functions or under program control.

Load Address Key
(ADDR LOAD)

This key loads the contents of the Switch Register into the CPMA and forces Fetch to be set (no Major States while the Load Address Key is depressed).

Extended Address Load
(EXTD ADDR LOAD)

This switch loads the contents of SR(6–11) into the Data Field and Instruction Field registers of the Memory Extension Control. SR(9–11) goes to Data Field 0–2, SR(6–8) goes to Instruction Field 0–2.

Clear Key (CLEAR)

This key issues an Initialize Pulse, clearing the AC, Link, Interrupt system, and I/O Flags.

Continue Key (CONT)

This key resumes the computer program by issuing a Memory Start and setting the Run flip-flop. The word stored at the address currently held by the CPMA is taken as the first instruction.

Examine Key (EXAM)

Puts the contents of core memory at the address specified by the contents of the CPMA into the MB. Then the contents of the PC and CPMA are incremented by one to allow examination of the contents of sequential core memory addresses by repeating the operation of the Examine switch.

Halt Switch (HALT)

This switch clears the Run flip-flop and and causes the machine to stop at TS1 of the next Fetch cycle. This switch is also used for single instruction stepping.

Single Step Switch
(SING STEP)

This switch clears the Run flip-flop and causes the machine to stop at TS1 of the next cycle. Thereafter, repeated depressing of the Continue key steps the program one cycle at a time, so that the contents of registers can be observed in each state.

Deposit Key (DEP)

Loads the contents of the SR into the MB and core memory at the address given by the current contents of the CPMA. Then the contents of the PC and CPMA are incremented by one. This allows storing of information in sequential memory addresses by repeated operation of the Deposit switch.

Indicator Selector Switch

This is a six-position rotary switch, used to select a register for display. The six positions are as follows:

STATE — Indicates an individual function for each bit:

0	Fetch
1	Defer
2	Execute
3	Instruction Register 0
4	Instruction Register 1
5	Instruction Register 2
6	MD DIR
7	Data Control
8	SW
9	Pause
10	Break in Prog
11	Break

STATUS — Indicates an individual function each bit:

0	Link
1	Greater Than Flag
2	Interrupt Bus
3	No Interrupt Allowed
4	Interrupt On
5	User Mode
6	Instruction Field 0
7	Instruction Field 1
8	Instruction Field 2
9	Data Field 0
10	Data Field 1
11	Data Field 2

AC — Indicates bits 0–11 of the Accumulator at TS1.
MD — Indicates information just written or rewritten into memory.
MQ — Indicates contents of MQ register during TS1.
BUS — Indicates bis 0–11 of the DATA lines.

Memory Address

Indicates the contents of the memory address which will be accessed next.

EMA

Indicates which Extended Memory field is being accessed.

Run Light

When lit means machine’s timing is enabled and capable of executing instructions.

Limitations and extensions of the simulated KC8-EA Programmer’s Console

The simulated KC8-EA has some limitations and extensions compared to a hardware KC8-EA:

The console is able to simulate single step execution. This simulation is done console internally because the PDP-8/E Simulator itself performs PDP-8/E instructions atomically. While executing a Fetch and Defer memory cycle, no state changes occur in the simulators PDP-8/E, only the display lights of the console reflect the accompanying state changes. When the final Execute memory cycle (or, for single cycle instructions, e. g. OPRs, the Fetch cycle) is performed, the simulators PDP-8/E is instructed by the console to perform the complete PDP-8/E instruction at once. So, while the console is in a Defer or Execute state, there may be inconsistencies between the register values visible in the CPU window and the corresponding values displayed by the KC8-EA. To avoid confusion, it is suggested not to alternately use single step execution of the console and the instruction stepping of the simulator.
When the user depresses the Single Step switch while the PDP-8/E is running, it halts at TS1 of a Fetch cycle, like with the Halt switch, and not at TS1 of any memory cycle. When the Single Step or Halt switch is down, the simulator can’t be started in Step, Trace or Go mode.
When the machine is in single instruction mode (Halt switch down) and an interrupt is pending, depressing the Continue switch once brings the simulator to the first instruction of the interrupt service routine at location 1. On a real PDP-8/E, the switch must be operated twice to reach this state. When the interrupt is caused by a privileged instruction executed in user mode, the simulator halts after the privileged instruction, a hardware PDP-8/E halts at location 0. The next operation of the Continue switch brings both the simulator and a real PDP-8/E to the first instruction of the interrupt service routine at location 1. This different behaviour is also present when stepping on memory cycle level (Single Step switch down).
The state of the SW switch is not directly available for other I/O devices. But whenever the user operates this switch, a Cocoa notification with the name “kc8eaSWChangedNotification” is posted; the notification object is a number representing the state of the switch, 0 for down and 1 for up.
Turning the Power key to OFF quits the PDP-8/E Simulator.
When the PDP-8/E is running, the display lights are sampled with a frequency of 60 Hz. They then display the state at the end of the Fetch cycle, before the instruction is actually executed, of the next PDP-8/E instruction to be performed; so the STATE display display can indicate Defer and Execute cycles.
At least in the following points the display differs from a hardware PDP-8/E:
- The DATA CONT, BRK PROG and BRK indicators of the STATE display are always off.
- The PAUSE indicator of the STATE display may be inprecise.
- The NO INT indicator of the STATUS display is illuminated when the Interrupt Delay or Interrupt Inhibit flag is set. On a hardware PDP-8/E, this indicator is derived from signals not available with the PDP-8/E Simulator.
- The BUS display may be inprecise under certain circumstances, e. g. for group 3 OPRs of the EAE or for IOT instructions, where always the AC is shown.
- The MD display does not reflect the additional memory access of EAE two word instructions.
- When the PDP-8/E halts from the Step, Trace or Go mode of the simulator, the STATE, MD and BUS display may be inprecise. E. g. the MD DIR is always turned on, MD shows the opcode of the last instruction executed, but not the memory references eventually performed by the instruction. (When you execute single PDP-8/E instructions by pressing the Continue key of the console while the Halt switch is down, the display is more precise because then the KC8-EA internally simulates the Fetch, Defer and Execute cycle of the instruction.)

The console keys and switches can be operated using the following keyboard shortcuts:

⌥w	Operate the SW switch
⌥0,…,⌥9, ⌥a, ⌥b	Operate the corresponding switch of the Switch Register
⌥l	Operate the Load Address key
⌥x	Operate the Extended Address Load key
⌥c	Operate the Clear key
⌥t	Operate the Continue key
⌥e	Operate the Examine key
⌥h	Operate the Halt switch
⌥s	Operate the Single Step switch
⌥d	Operate the Deposit key
⌥<	Turn the Indicator Selector switch anticlockwise
⌥>	Turn the Power key clockwise