165 lines
5.3 KiB
C
165 lines
5.3 KiB
C
#include "spi.h"
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/*-------------------------------------------------------------------------*/
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/* Platform dependent macros and functions needed to be modified */
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/*-------------------------------------------------------------------------*/
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#define CS_H() bset(P0) /* Set MMC CS "high" */
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#define CS_L() bclr(P0) /* Set MMC CS "low" */
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#define CK_H() bset(P1) /* Set MMC SCLK "high" */
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#define CK_L() bclr(P1) /* Set MMC SCLK "low" */
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#define DI_H() bset(P2) /* Set MMC DI "high" */
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#define DI_L() bclr(P2) /* Set MMC DI "low" */
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#define DO btest(P3) /* Test MMC DO (high:true, low:false) */
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// Command listing
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/* T16: Transfer 16-bit
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* First, the 16-bit value encoded in the address bits A[17:2] is latched.
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* The data output mux is set to the current RXR and the cycle completes.
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* Shortly after /AS rises, the SPI transfer engine begins
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* transferring the latched value.
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*/
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/* T16S: Transfer 16-bit Swapped
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* Same as T16L but read data is byte-swapped.
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*/
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/* MERT: Measure Elapsed time and Reset Timer
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* The elapsed time since the last MERT command is returned in D[31:24]
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* and the timer is reset.
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*/
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/* SKIP1: Skip Clocks with MOSI "1"
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*
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*/
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/* SKIP0: Skip Clocks with MOSI "0"
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*
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*/
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/* T8S: Transfer 8-bit Swapped
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* Same as T8 but read data is byte-swapped.
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*/
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/* T8: Transfer 8-bit
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* First, the 8-bit value encoded in the address bits A[9:2] is latched.
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* The data output mux is set to the current RXR and the cycle completes.
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* Shortly after /AS rises, the SPI transfer engine begins
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* transferring the latched value.
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*/
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/* WRC: Write Command
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* The command encoded in address bits A[9:2] is sent to the command target
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* corresponding to the address bits A[15:10].
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* Command targets:
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* $00 - Set bitbang
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* A[2] - SCS value
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*/
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/* RDRXR: Read Receive Data Register
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* The the current RXR is returned in D[31:16] and the cycle completes.
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*/
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/* RDRXRS: Read Receive Data Register Swapped
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* Same as RDRXR but read data is byte-swapped.
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*/
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/* MAGIC: Write Command
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* Write sequence $FF $00 $55 $AA $C1 $AD
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* to enable registers at $40890000-$4097FFFF.
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* Write anything else to disable them.
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* Always reads 0xC1AD
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*/
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// SPI controller address map:
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// 40940000-4097FFFF (256 kB, D[31:16]) T16S. Write transfer data in A[17:2].
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// 40900000-4093FFFF (256 kB, D[31:16]) T16. Write transfer data in A[17:2].
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// 408C0000-408FFFFF (320 kB) reserved
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// 408A0000-408AFFFF ( 64 kB, D[31:24]) WRC. Write port address in A[15:10] and data in A[9:2].
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// 40891C00-4089FFFF ( 55 kB) reserved
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// 40892000-408923FF ( 1 kB, D[31:24]) MERT.
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// 40891C00-40891FFF ( 1 kB) SKIP1. Write bytes to skip in A[9:2].
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// 40891800-40891BFF ( 1 kB) SKIP0. Write bytes to skip in A[9:2].
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// 40891400-408917FF ( 1 kB, D[31:16]) T8S. Write transfer data in A[9:2].
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// 40891000-408913FF ( 1 kB, D[31:16]) T8. Write transfer data in A[9:2].
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// 40890C00-40890FFF ( 1 kB, D[31:16]) RDRXRS.
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// 40890800-40890BFF ( 1 kB, D[31:16]) RDRXR.
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// 40890400-408907FF ( 1 kB) reserved
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// 40890000-408903FF ( 1 kB, D[31:24]) MAGIC. Write magic numbers in A[9:2].
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// 40880000-408FFFFF ( 64 kB, D[31:00]) ROMBUS driver data
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#define RB_T16S(x) (*(volatile int*) (0x40940000 + ((x && 0xFFFF)<<02)) )
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#define RB_T16(x) (*(volatile int*) (0x40900000 + ((x && 0xFFFF)<<02)) )
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#define RB_RDS(a) (*(volatile char*) (0x408B0000 + ((a && 0x003F)<<10)) )
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#define RB_WRC(a,d) (*(volatile char*) (0x408A0000 + ((a && 0x003F)<<10)
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+ ((d && 0x00FF)<<02)) )
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#define RB_MERT(x) (*(volatile char*) (0x40892000 + ((x && 0xFFFF)<<02)) )
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#define RB_SKIP1(n) (*(volatile char*) (0x40891C00 + ((x && 0xFFFF)<<02)) )
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#define RB_SKIP0(n) (*(volatile char*) (0x40891800 + ((x && 0xFFFF)<<02)) )
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#define RB_T8S(x) (*(volatile int*) (0x40891400 + ((x && 0xFFFF)<<02)) )
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#define RB_T8(x) (*(volatile int*) (0x40891000 + ((x && 0xFFFF)<<02)) )
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#define RB_RDRXRS (*(volatile int*) (0x40890C00 + ((x && 0xFFFF)<<02)) )
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#define RB_RDRXR (*(volatile int*) (0x40890800 + ((x && 0xFFFF)<<02)) )
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#define RB_WRMOSI(x) (*(volatile char*) (0x40890400 + ((x && 0x0001)<<02)) )
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#define RB_MAGIC(x) (*(volatile char*) (0x40890000 + ((x && 0xFFFF)<<02)) )
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#define SPI_GET_MISO(d) (d & 1)
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void spi_select() {
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ret = *SPI_CMD_SEL0;
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ret = *SPI_CMD_SEL1;
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ret = *SPI_CMD_SEL2;
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ret = *SPI_CMD_SEL3;
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}
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void spi_deselect() {
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ret = *SPI_CMD_DES0;
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ret = *SPI_CMD_DES1;
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ret = *SPI_CMD_DES2;
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ret = *SPI_CMD_DES3;
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}
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void spi_tx_slow(char d) {
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for (int i = 0; i < 8; i++) {
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*SPI_CMD_BBA((0 & 0x02) | (d & 0x01));
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*SPI_CMD_BBA((1 & 0x02) | (d & 0x01));
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d >>= 1;
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}
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*SPI_CMD_BBA((0 & 0x02) | (0 & 0x01));
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}
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char spi_rx_slow() {
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char ret = 0;
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for (int i = 0; i < 8; i++) {
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*SPI_CMD_BBA((0 & 0x02) | (1 & 0x01));
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*SPI_CMD_BBA((1 & 0x02) | (1 & 0x01));
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ret = (ret << 1) + (*SPI_CMD_BBA((1 & 0x02) | (1 & 0x01)) & 1);
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}
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return ret;
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}
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void spi_skip_slow(int n) {
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while (n-- > 0) {
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for (int i = 0; i < 8; i++) {
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*SPI_CMD_BBA((0 & 0x02) | (1 & 0x01));
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*SPI_CMD_BBA((1 & 0x02) | (1 & 0x01));
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}
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}
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*SPI_CMD_BBA((0 & 0x02) | (1 & 0x01));
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}
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void spi_tx_8(char d) {
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*SPI_CMD_SH8(d);
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}
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char spi_rx_8() {
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*SPI_CMD_SH8(0xFF);
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return *SPI_CMD_RD & 0xFF;
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}
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void spi_tx_16(int d) {
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*SPI_CMD_SH16(d);
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}
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int spi_rx_16() {
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*SPI_CMD_SH16(0xFFFF);
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return *SPI_CMD_RD & 0xFFFF;
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}
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void spi_skip(int n) {
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while (n-- > 0) {
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for (int i = 0; i < 8; i++) {
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*SPI_CMD_SH8(0xFF);
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}
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}
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}
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