Bring in CubeE sources

Resource forks are included only for .rsrc files. These are DeRezzed into their data fork. 'ckid' resources, from the Projector VCS, are not included.

The Tools directory, containing mostly junk, is also excluded.
This commit is contained in:
Elliot Nunn 2017-09-17 17:09:04 +08:00
commit 5b0f0cc134
1820 changed files with 1351740 additions and 0 deletions

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#
# File DeclData.make
#
# Contains: Makefile for Declaration ROM.
#
# Written by: Kurt Clark, Chas Spillar, and Tim Nichols
#
# Copyright: © 1992-1993 by Apple Computer, Inc., all rights reserved.
#
# Change History (most recent first):
#
# <SM5> 12/13/93 PN Roll in Kaos and Horrors code to support AJ and Malcom machines.
# <SM4> 9/9/93 pdw Added slots.a to dependencies.
# <SM3> 08-03-93 jmp Added various necessary dependencies that werenÕt previously
# spelled out.
# <SM2> 3/4/93 dwc Added DeclDataPDMMace definition for PDM ENET.
# <1> 2/21/93 kc first checked in
# <SM2> 12-04-92 jmp Added the rules for building VSC (Keystone) DeclData.
EthernetDir = {DeclDir}DeclNet:
SonicDir = {EthernetDir}Sonic:
MaceDir = {EthernetDir}Mace:
VideoDir = {DeclDir}DeclVideo:
GammaDir = {VideoDir}Gamma:
PDMMaceDir = {MaceDir}PDMMaceEnet:
#include {MaceDir}Mace.Make
#include {SonicDir}Sonic.Make
#include {VideoDir}VideoDrivers.Make
#include {PDMMaceDir}PDMEnet.Make
DeclResources = "{RsrcDir}DeclData.rsrc" ¶
"{RsrcDir}PrimaryInit.rsrc" ¶
"{RsrcDir}SecondaryInit.rsrc" ¶
"{RsrcDir}SuperInit.rsrc" ¶
"{RsrcDir}DeclDataMace.rsrc" ¶
"{RsrcDir}DeclDataPDMMace.rsrc" ¶
"{RsrcDir}DeclDataSonic.rsrc" ¶
"{RsrcDir}DeclDataVideo.rsrc" ¶
"{RsrcDir}Gamma.rsrc"
DeclHeaders = "{ObjDir}StandardEqu.d" ¶
"{AIncludes}GestaltEqu.a" ¶
"{AIncludes}ShutDown.a" ¶
"{AIncludes}ROMEqu.a" ¶
"{AIncludes}Video.a" ¶
"{IntAIncludes}DockingEqu.a" ¶
"{IntAIncludes}EgretEqu.a" ¶
"{IntAIncludes}GestaltPrivateEqu.a" ¶
"{IntAIncludes}HardwarePrivateEqu.a" ¶
"{IntAIncludes}IOPrimitiveEqu.a" ¶
"{IntAIncludes}PowerPrivEqu.a" ¶
"{AIncludes}Slots.a" ¶
"{IntAIncludes}SlotMgrEqu.a" ¶
"{IntAIncludes}UniversalEqu.a" ¶
"{IntAIncludes}DepVideoEqu.a" ¶
"{SonicDir}SonicEqu.a"
#
# DeclData
#
"{RsrcDir}DeclData" Ä {DeclResources} "{RsrcDir}RomLink"
"{RsrcDir}RomLink" {DeclResources} -o "{Targ}"
"{RsrcDir}DeclData.rsrc" Ä "{RIncludes}Types.r" ¶
"{IntRIncludes}DepVideoEqu.r" ¶
"{IntRIncludes}HardwarePrivateEqu.r" ¶
"{IntRIncludes}InternalOnlyEqu.r" ¶
"{IntRIncludes}QuickDraw.r" ¶
"{IntRIncludes}ROMLink.r" ¶
"{DeclDir}DeclData.r"
Rez {StdROpts} "{DeclDir}DeclData.r" -o "{Targ}"
# The ROMLinkHeaderBuilder tool is not used.
#"{IntRIncludes}ROMLink.r" Ä "{RsrcDir}ROMLinkHeaderBuilder"
# "{RsrcDir}ROMLinkHeaderBuilder" > {Targ} #This is kinky
#
# PrimaryInit
#
"{RsrcDir}PrimaryInit.rsrc" Ä "{ObjDir}PrimaryInit.a.o"
Link {StdLOpts} {StdAlign} -rt decl=200 "{ObjDir}PrimaryInit.a.o" -o "{Targ}"
"{ObjDir}PrimaryInit.a.o" Ä "{DeclDir}PrimaryInit.a" ¶
{DeclHeaders}
Asm {StdAOpts} -d ForEclipseROM=0,sonic32=1,ctlpad=0,mmu=1 -i "{SonicDir}" "{DeclDir}PrimaryInit.a" -o "{Targ}"
#
# SecondaryInit
#
"{RsrcDir}SecondaryInit.rsrc" Ä "{ObjDir}SecondaryInit.a.o"
Link {StdLOpts} {StdAlign} -rt decl=210 "{ObjDir}SecondaryInit.a.o" -o "{Targ}"
"{ObjDir}SecondaryInit.a.o" Ä "{DeclDir}SecondaryInit.a" ¶
{DeclHeaders}
Asm {StdAOpts} -d ForEclipseROM=0,sonic32=1,ctlpad=0,mmu=1 -i "{SonicDir}" "{DeclDir}SecondaryInit.a" -o "{Targ}"
#
# SuperInit
#
"{RsrcDir}SuperInit.rsrc" Ä "{ObjDir}SuperInit.a.o"
Link {StdLOpts} {StdAlign} -rt decl=220 "{ObjDir}SuperInit.a.o" -o "{Targ}"
"{ObjDir}SuperInit.a.o" Ä "{DeclDir}SuperInit.a" ¶
{DeclHeaders}
Asm {StdAOpts} -d ForEclipseROM=0,sonic32=1,ctlpad=0,mmu=1 -i "{SonicDir}" "{DeclDir}SuperInit.a" -o "{Targ}"
#
# Ethernet
#
"{ObjDir}Loopback.c.o" Ä "{EthernetDir}Loopback.c" ¶
"{CIncludes}TextUtils.h" ¶
"{CIncludes}Memory.h" ¶
"{CIncludes}Devices.h" ¶
"{CIncludes}Files.h" ¶
"{CIncludes}AppleTalk.h" ¶
"{CIncludes}OSUtils.h"
C {StdCOpts} -b -o "{Targ}" "{EthernetDir}Loopback.c"
#
# Gamma Resource
#
"{RsrcDir}Gamma.rsrc" Ä "{RIncludes}Types.r" ¶
"{IntRIncludes}ROMLink.r" ¶
"{GammaDir}Gamma.r"
Rez {StdROpts} "{GammaDir}Gamma.r" -o "{Targ}"

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DeclData/DeclNet/802Equ.a Normal file
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;
; File: 802Equ.a
;
; Contains: Equates for IEEE network standards
;
; Written by: Kerry E. Lynn, Sean Findley
;
; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved.
;
; Change History (most recent first):
;
; <1> 10/6/92 GDW New location for ROMLink tool.
; <1> 3/26/92 FM first checked in
; <1> 12/14/90 JK Added to build
;
; To Do:
;
;-----------=-----------=-------------------------------=---------------------------------------
; 802Equ.a - Equates for IEEE network standards
;
; Kerry E. Lynn
; Feb 1989
;
; Copyright (C) 1989 by:
;
; Apple Computer, Inc.
; 20525 Mariani Ave.
; Cupertino, CA 95014
;
; All Rights Reserved.
;-----------=-----------=-------------------------------=---------------------------------------
; 24-bit quantities, left justified
AppleCode EQU $08000700 ; Apple's vendor code for 802.2 Individual addr
MultiCode EQU $09000700 ; Apple's vendor code for 802.2 Group addr
; Size of a MAC addr
MACAddrSz EQU 6 ; max size (in bytes) for data link addr
MaxMCastSz EQU MACAddrSz ; max size (in bytes) for multicast addr
;---------------------------------------
; 802.3 MAC packet header
;---------------------------------------
MDstAddr EQU 0 ; Offset to destination address
MSrcAddr EQU MDstAddr+MACAddrSz ; Offset to source address
MLength EQU MSrcAddr+MACAddrSz ; Offset to LLC length
MHdrSize EQU MLength+2 ; 802.3 MAC header size
;---------------------------------------
; 802.2 LLC (Type 1) packet header
;---------------------------------------
LDSAP EQU 0 ; Offset to destination Service Access Point (SAP)
IGBIT EQU 0 ; I/G = 0 if Individual DSAP, = 1 if Group DSAP
LSSAP EQU LDSAP+1 ; Offset to source SAP
CRBIT EQU 0 ; C/R = 0 if Command, = 1 if Response
LCtrl EQU LSSAP+1 ; Offset to LLC CONTROL field (see below)
LHdrSize EQU LCtrl+1
LInfo EQU LHdrSize ; Offset to LLC Information
GlobalSAP EQU $FF
NullSAP EQU 0
;---------------------------------------
; CONTROL field bits for 802.2 Type 1 LLC Protocol Data Units (PDUs)
;---------------------------------------
UI EQU %00000011 ; value for "Unnumbered Information" (P/F bit must be 0)
XID EQU %10101111 ; mask for "Exchange Identification" (P/F bit may be 0 or 1)
TEST EQU %11100011 ; mask for "Test" (P/F bit may be 0 or 1)
PFBIT EQU 4 ; P/F = 0 if Poll (command), = 1 if Final (response)
;---------------------------------------
; XID information field
;---------------------------------------
XIDformat EQU %10000001 ; indicates IEEE basic format
XIDinfo1 EQU %00000001 ; indicates Type 1 AND Class I LLC
XIDinfo2 EQU %00000000 ; receive window size = N/A
XIDinfoSz EQU 3 ; number of bytes in an XID response
;---------------------------------------
; Sub-Network Access Protocol (SNAP) packet header
;---------------------------------------
SType EQU 0 ; 5-byte protocol discriminator
SHdrSize EQU SType+5

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;
; File: ATMacros.a
;
; Contains: Assembly macros used by AppleTalk
;
; Written by: Mike Shoemaker
;
; Copyright: © 1990-1993 by Apple Computer, Inc., all rights reserved.
;
; Change History (most recent first):
;
; <SM2> 12/13/93 PN Roll in KAOS and Horror to add support for Malcom and AJ
; <1> 10/6/92 GDW New location for ROMLink tool.
; <SM2> 6/22/92 mal Added some labels to VERSION macro and added VMImmumebit equate.
; <SM3> 5/4/92 CSS moved to ethernet folder to get build to work
; <2> 3/19/92 kc Roll in Terror/Horror Changes.
; <SM1> 2/??/92 kc first checked in
; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
; Pre-SuperMario ROM comments begin here.
; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
; <H2> 01/22/92 jmp (BG,Z2) Added some additional macros for new ethernet changes.
; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
; Pre-Horror ROM comments begin here.
; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
; <T1> 3/27/91 jmp first checked in
; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
; Pre-TERROR ROM comments begin here.
; ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
; <8> 1/30/91 mbs cj,#82011: Move years after company name in copyright message.
; <7> 12/17/90 mbs The ALIGN directive does not work for the IIGS assembler. Use
; IF ENDIF to generate an extra dc.b 0 if necessary. Yes except
; for the ALIGN, the entire macro worked under the IIGS
; assembler!.
; <6> 11/28/90 mbs In the VERSION macro, when the release stage is 'released', pad
; the version with two trailing spaces so that the length remains
; the same when changing from an f1 to a Golden Master build.
; <5> 11/26/90 mbs Did not handle 3-digit major version number
; <4> 11/12/90 mbs Steven pointed out that verUs is zero, not 1.
; <3> 11/10/90 mbs Add optional parameter to set the label at the front of the
; version structure.
; <2> 11/09/90 mbs Add 'v' in front of version number in long string
; 11/9/90 mbs First written
;
; To Do:
;
; WARNING -- CAN'T USE IF (__IncludingATalkMacros__ == 'UNDEFINED') because
; 6502 assember barfs and doesn't include the file.
PRINT PUSH, OFF
;==========================================================================================
; VERSION
;
; USAGE:
; VERSION <Name>, <Major Version>, <Minor Version>,
; <release stage>, <Revision level>,
; <Copyright Years> [, <Engineering Suffix> [, <Version Label> ] ]
;
; The name field should be quoted if more than one word.
; The copyright years field may or may not be quoted. The macro works either way
; It is OK to leave the engineering suffix field empty.
;
; The start of the version information is given the Label 'VersionInfo', unless
; you specify the last parameter; then it will be used. It must not be quoted.
;
; Example for EtherTalk 1.2a3q1 copyrighted 1987-1990
;
; VERSION 'EtherTalk', 1, 2, 0, alpha, 3, '1987-1990', 'q1'
;==========================================================================================
ATM_development EQU $20 ; These are used in the 3rd byte of the 4-byte version #
ATM_alpha EQU $40 ; .. to indicate release stage
ATM_beta EQU $60
ATM_final EQU $80
ATM_release EQU $80
ATM_verUS EQU 0
MACRO
VERSION &sName, &nMajor, &nMinor, &nBug, \
&sStage, &nRevision, &sCopyright, &sEngr='', &sLabel0=VersionInfo,&sLabel1=End
&sLabel0 ;Make label for this version information
LCLA &nStage ;Numeric representation of stage
LCLC &cStage ;Character representation of stage
LCLA &nPadBytes ;Add padding at end of record to <K2>
;allow room for expansion if we <K2>
;have to add bug release digits <K2>
;to the version # <K2>
LCLC &StrSetting ;To save current string setting
&StrSetting SETC &SETTING('STRING') ;Save current string setting
STRING PASCAL ;Set string state to Pascal
;
; Do some error checking
;
IF &UPCASE(&sStage)='ALPHA' THEN
&nStage SETA ATM_alpha
&cStage SETC 'a'
ELSEIF &UPCASE(&sStage)='BETA' THEN
&nStage SETA ATM_beta
&cStage SETC 'b'
ELSEIF &UPCASE(&sStage)='DEVELOPMENT' THEN
&nStage SETA ATM_development
&cStage SETC 'd'
ELSEIF &UPCASE(&sStage)='FINAL' THEN
&nStage SETA ATM_final
&cStage SETC 'f'
ELSEIF &UPCASE(&sStage)='RELEASE' THEN
&nStage SETA ATM_release
&cStage SETC 'x'
ELSE
AERROR 'The stage parameter to VERSION must be: development, alpha, beta, final or release'
ENDIF
IF (&nMinor > 15) THEN
AERROR 'The Minor version must be less than 16'
ENDIF
IF (&nBug > 15) THEN
AERROR 'The Bug fix version must be less than 16'
ENDIF
;
; Generate the 4-byte version numbers
;
dc.b &nMajor ;Major version number
dc.b (&nMinor * 16) + &nBug ;Build 2nd byte of version
dc.b &nStage, &nRevision ;stage and revision level
;
; Generate the integer country code
;
dc.w ATM_verUS ;Country Code
;
; Build Version string from major/minor version string
;
LCLC &lShortVer
;
; Make 1st digit of version string
;
IF (&nMajor >= 100) THEN
&lShortVer SETC &CONCAT(&CHR(&nMajor / 100 + $30), \
&CHR((&nMajor MOD 100) / 10 + $30), \
&CHR(&nMajor MOD 10 + $30))
ELSE
IF (&nMajor >= 10) THEN
&lShortVer SETC &CONCAT(&CHR(&nMajor / 10 + $30), &CHR(&nMajor MOD 10 + $30))
ELSE
&lShortVer SETC &CHR(&nMajor + $30)
ENDIF
ENDIF
;
; Append 2nd digit of version number (ie: 1.0)
;
IF (&nMinor >= 10) THEN
&lShortVer SETC &CONCAT(&lShortVer,'.',&CONCAT(&CHR(&nMinor / 10 + $30), &CHR(&nMinor MOD 10 + $30)))
ELSE
&lShortVer SETC &CONCAT(&lShortVer,'.',&CHR(&nMinor + $30))
ENDIF
;
; Append third digit of version number if non-zero (ie: 1.0.2). If zero, leave <K2>
; room for the extra characters at the end of the record <K2>
;
IF (&nBug <> 0) THEN
&nPadBytes SETA 0 ; Will not need padding <K2>
IF (&nBug >= 10) THEN
&lShortVer SETC &CONCAT(&lShortVer,'.',&CONCAT(&CHR(&nBug / 10 + $30), &CHR(&nBug MOD 10 + $30)))
ELSE
&lShortVer SETC &CONCAT(&lShortVer,'.',&CHR(&nBug + $30))
ENDIF
ELSE
&nPadBytes SETA 1 ; Leave room for padding <K2>
ENDIF
; Append stage letter and revision if not a release version.
; For release version, append two spaces. This way the string does not change length
; between an 'f1' build and a GM build.
IF (&cStage <> 'x') THEN
&lShortVer SETC &CONCAT(&lShortVer,&cStage)
IF (&nRevision >= 10) THEN
&lShortVer SETC &CONCAT(&lShortVer,&CONCAT(&CHR(&nRevision / 10 + $30), &CHR(&nRevision MOD 10 + $30)))
ELSE
&lShortVer SETC &CONCAT(&lShortVer,&CHR(&nRevision + $30))
ENDIF
ELSE
&lShortVer SETC &CONCAT(&lShortVer, ' ') ; Append two spaces if release
ENDIF
;
; Emit the short string
;
dc.b '&lShortVer'
; ALIGN directive doesn't exist on IIGS assembler so do it the hard way...
IF ((&LEN(&lShortVer) +1) MOD 2) = 1 THEN
dc.b 0
ENDIF
;
; Trim the beginning and ending quotes from the name, copyright years, and
; engineering suffix if present
;
LCLC &lName
LCLC &lCopyright
LCLC &lEngr
IF &SUBSTR(&sName, 1, 1) = &CHR($27) THEN
&lName SETC &SUBSTR(&sName, 2, &LEN(&sName) - 2)
ELSE
&lName SETC &sName
ENDIF
IF &SUBSTR(&sCopyright, 1, 1) = &CHR($27) THEN
&lCopyright SETC &SUBSTR(&sCopyright, 2, &LEN(&sCopyright) - 2)
ELSE
&lCopyright SETC &sCopyright
ENDIF
IF &SUBSTR(&sEngr, 1, 1) = &CHR($27) THEN
&lEngr SETC &SUBSTR(&sEngr, 2, &LEN(&sEngr) - 2)
ELSE
&lEngr SETC &sEngr
ENDIF
;
; Build the long string
;
LCLC &lLongVer ; Define a local variable to hold it
&lLongVer SETC &CONCAT(&lName,' v',&lShortVer,&lEngr,'; © Apple Computer, Inc. ',&lCopyright)
;
; Emit the long string
;
LCLC &sLongVerLabel ;<K2 start>
LCLC &sLongVerLabelEnd ;
&sLongVerLabel SETC &CONCAT(&sLabel0, 'LongStr') ;
&sLongVerLabel ;
dc.b '&lLongVer' ;
IF ((&LEN(&lLongVer) +1) MOD 2) = 1 THEN ; Align things
dc.b 0
ENDIF
;
; If this is an "xx.x" release rather than an "xx.x.x" release, leave room so that
; if we have to rev the version # to x.x.x, the size of the record will not change.
;
IF (&nPadBytes) THEN
dc.b 0,0,0,0
ENDIF
&sLongVerLabelEnd SETC &CONCAT(&sLongVerLabel, 'End')
&sLongVerLabelEnd
;
; Clean up and we're done
;
LCLC &sEndLabel ;Make label for end of version information
&sEndLabel SETC &CONCAT(&sLabel0, &sLabel1)
&sEndLabel
STRING &StrSetting ;Restore string setting
ENDM
EJECT
;==========================================================================================
; SCCLOCKOUT
;
; Macro for disabling interrupts.
;==========================================================================================
SRIntMaskBits EQU $0700 ; The 3 interrupt level bit in the SR
SRIntMaskBitsCMP EQU $F8FF ; The 3 interrupt level bit in the SR
SRIntLevel6 EQU $0600 ; Level 6 interrupt mask
SRIntLevel6MASK EQU $FEFF ; Level 6 interrupt AND value
SRIntLevel5MASK EQU $FDFF ; Level 5 interrupt AND value <K2>
MACRO
_SCCLOCKOUT
ORI.W #SRIntMaskBits,SR ; Set all of the INT bits
ANDI.W #SRIntLevel6MASK,SR ; Set to priority 6
ENDM
;==========================================================================================
; _SETINTMASK
;
; Macro for setting the interrupt level to an arbitrary level. Pass the level in
; a Data register.
;==========================================================================================
MACRO
_SETINTMASK &sReg
move.w SR,-(SP)
andi.w #SRIntMaskBitsCMP,(SP)
or.w &sReg,(SP)
move.w (SP)+,SR
ENDM
;==========================================================================================
; VSCCEnable
;
; Macro for disabling interrupts.
; Pass address register holding MPP vars, and a temporary Data register
;==========================================================================================
MACRO
_VSCCENABLE &sMPPVarsReg, &tmpReg
MOVE.W SR, &tmpReg
ANDI.W #SRIntMaskBitsCMP,&tmpReg ; Clear all of the INT bits
EORI.W #$2000, &tmpReg ; Toggle the 2000 bit
move.w vSCCEnable(&sMPPVarsReg),-(SP) ; Push vscc enable
EOR.W &tmpReg, (SP) ; Or in the int bits (and toggles 2000)
; Stupid machine won't let memory be the source on an XOR instruction
MOVE.W (SP)+,SR ; Set SR
ENDM
;==========================================================================================
; These Macros & Equates are used to call the multipurpose function dispatcher in the
; Lap Manager. None of these functionn have jack to do with the Lap Manager, but they
; provide a way for code to get the functions without having to link with the library
; containing them. Of course, they require that a Lap Manager be present.
;==========================================================================================
;
; Macro used in following macros
;
MACRO
_L21Common &nVal
LCLC &cLabel ; Used to make a semi-unique label
&cLabel SETC &CONCAT('@L21Ret',&nVal)
pea &cLabel ; Want to return to here
move.l LAPMgrPtr,D0 ; Ptr to Lap Manager
add.l #LAPMgrCall,D0 ; Ptr to dispatch entry point
move.l D0,-(SP) ; Put on stack
move.l #((&nVal << 16) + LInt21Dispatch),D0
rts ; Call Lap Manager
&cLabel
ENDM
;
; Macros to call Lap Manager Dispatch routines
;
; Returns non-zero in D0.L if Extensions are disabled at boot time. Always returns zero on
; System 6. Sets condition codes
MACRO
_LExtensionsDisabled
_L21Common L21ExtensionsDisabled
ENDM
; pascal Handle GetBestResource(OSType theType, short theID)
MACRO
_LGetBestResource
_L21Common L21GetBestResource
ENDM
; pascal Boolean TrapAvailable(short theTrap)
MACRO
_LTrapAvailable
_L21Common L21TrapAvailable
ENDM
;==========================================================================================
; New Macros go here
;==========================================================================================
;
; MACROS for SNMP counters <K2>
;
MACRO
_IncrCount &SNMPCounter
ADDQ.L #1, SNMPVars.&SNMPCounter(A2) ; increment whatever SNMP counter
ENDM
VMImmuneBit EQU 0 ; bit in driver DCE flags to tell VM to leave paramblocks alone
PRINT POP
; END ATMacros.a

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;
; File: ENETEqu.a
;
; Contains: Equates for the Ethernet driver
;
; Written by: Sean Findley (Version 1.1a1)
;
; Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved.
;
; This file is used in these builds: Mac32
;
; Change History (most recent first):
;
; <SM2> 10/26/92 mal Updated SNMP control codes.
; <1> 10/6/92 GDW New location for ROMLink tool.
; <2> 3/26/92 FM Rolled into reality
; <2> 1/9/91 JK Cleaned up to simplify N&C support.
; <1> 12/14/90 JK Added to build
;
; To Do:
;
IF (&TYPE('MHdrSize') = 'UNDEFINED') THEN
INCLUDE '802Equ.a' ; IEEE equates
ENDIF
; Control codes.
ESetGeneral EQU 253 ; Set "general" mode
EGetInfo EQU 252 ; Get info
ERdCancel EQU 251 ; Cancel read
ERead EQU 250 ; Read
EWrite EQU 249 ; Write
EDetachPH EQU 248 ; Detach protocol handler
EAttachPH EQU 247 ; Attach protocol handler
EAddMulti EQU 246 ; Add a multicast address
EDelMulti EQU 245 ; Delete a multicast address
EOpenSAP EQU 244 ; Open an 802.2 SAP
ECloseSAP EQU 243 ; Close an 802.2 SAP
ELapGetLinkStatus EQU 242 ; Get interface statistics, RFC 1213
EGetDot3CollStats EQU 241 ; Get 802.3 collision statistics, RFC 1284
EGetDot3Statistics EQU 240 ; Get 802.3 statistics, RFC 1284
ESetDot3Entry EQU 239 ; Set 802.3 status & control information
EGetDot3Entry EQU 238 ; Get 802.3 status & control information
FirstENET EQU EGetDot3Entry ; First ENET command
LastENET EQU ESetGeneral ; Last ENET command
; ENET queue element standard structure: arguments passed in the CSParam area
EProtType EQU CSParam ; Offset to protocol type code
EMultiAddr EQU CSParam ; Multicast address (EAddMulti,EDelMulti)
EHandler EQU EProtType+2 ; Offset to protocol handler
EWDSPointer EQU EHandler ; WDS pointer (EWrite)
EBuffPtr EQU EHandler ; Buffer pointer (ERead,EGetInfo)
EKillQEl EQU EHandler ; QEl pointer (ERdCancel)
EBuffSize EQU EBuffPtr+4 ; Buffer size (ERead,EGetInfo)
EDataSize EQU EBuffSize+2 ; Actual data size (Eread)
;---------------------------------------
; Ethernet packet header
;---------------------------------------
EDestAddr EQU 0 ; Offset to destination address
ESrcAddr EQU 6 ; Offset to source address
EType EQU 12 ; Offset to data link type
EHdrSize EQU 14 ; Ethernet header size
EMinDataSz EQU 46 ; Minimum data size
EMaxDataSz EQU 1500 ; Maximum data size
EAddrSz EQU 6 ; Size of an ethernet node address
MAddrSz EQU 8 ; Size of an ethernet multicast address (?)
; These are defined in 802Equ.a
;
ETHdrSize EQU MHdrSize+LHdrSize+SHdrSize
;
; Errors and misc.
;
eLenErr EQU ddpLenErr ; Length error
eMultiErr EQU ddpSktErr ; Multicast address error
EAddrRType EQU 'eadr' ; Alternate address resource type
;
; Link specific 'atlk' AGetInfo call
;
ESpeed EQU 10000000 ; Link speed in bits/sec

157
DeclData/DeclNet/Loopback.c Normal file
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/*
File: Loopback.c
Contains: Ethernet loopback test code
Written by: Sean Findley
Copyright: © 1990, 1992 by Apple Computer, Inc., all rights reserved.
Change History (most recent first):
<1> 10/6/92 GDW New location for ROMLink tool.
<SM5> 6/22/92 mal Modified so ptr and size to loopback test data is passed from
the driver since shared by Sonic and Mace drivers.
<SM1> 6/11/92 CS Roll-in changes from Reality:
<2> 6/1/92 DTY Include TextUtils.h for the new home of EqualString.
TextUtils now contains the EqualString prototype, so include it.
<3> 3/26/92 FM Rolled into reality
<2> 2/11/92 RB Use the real EqualString to avoid having to link old C libraries
with this code.
<2> 4/21/91 CCH Rolled in Sean Findley's changes.
<1> 12/14/90 JK Added to build
To Do:
*/
#include <TextUtils.h>
#include "memory.h"
#include "devices.h"
#include "files.h"
#include "appletalk.h"
#include "OSUtils.h"
typedef struct
{
char Addr[6];
} Enet;
typedef struct
{
Enet Destination; /* Ethernet destination */
Enet Source; /* Ethernet source */
unsigned short EProtocoltype; /* Ethernet protocol type */
char testdata[255];
} LBpacket;
typedef union /* parameter block for calling .ENET */
{
CntrlParam ctl; /* for ctl calls */
struct
{
char filler[28];
unsigned short EprotType;
Ptr EBuffPtr;
unsigned short EBuffSize;
unsigned short EDataSize;
} info;
MPPParamBlock ecall;
} Edrvrparms;
#define Ehandler DDP.DDPptrs.listener
#define EWdsPointer DDP.DDPptrs.wdsPointer
#define EKillQEl EBuffPtr
#define ERdCancel 251
#define ERead 250
#define EWrite 249
#define EDetachPH 248
#define EAttachPH 247
#define Ethhdrsz 14
Boolean cmpdata(char *p1, char *p2, short len) /* true = data equal, false = data not equal */
{
short i;
for(i=0;i<len;i++)
{
if(p1[i] != p2[i])
return(false);
}
return(true);
}
killtest(Edrvrparms *pbw, Edrvrparms *pb)
{
pbw->ctl.csCode = ERdCancel;
pbw->info.EKillQEl = (Ptr) pb;
PBControl((ParmBlkPtr) pbw,false);
pbw->ctl.csCode = EDetachPH;
PBControl((ParmBlkPtr) pbw,false);
}
Boolean LOOPBACKTEST(short refnum,Enet *enetaddr, int AppleData, short AppleDataSz)
{
LBpacket LBPR,LBPW;
Edrvrparms pb,pbw;
WDSElement wds[2];
unsigned long secs1,secs2;
pb.ctl.ioCRefNum = refnum;
pb.ctl.ioCompletion = nil;
pb.ctl.csCode = EAttachPH;
pb.info.EprotType = 0x809B;
pb.ecall.Ehandler = nil;
if (PBControl((ParmBlkPtr) &pb,false)) /* attach special protocol using default handler */
return(false);
pb.ctl.csCode = ERead;
pb.info.EBuffPtr = (Ptr) &LBPR;
pb.info.EBuffSize = sizeof(LBpacket);
if (PBControl((ParmBlkPtr) &pb,true)) /* setup a read using default handler */
{
pb.ctl.csCode = EDetachPH;
PBControl((ParmBlkPtr) &pb,false);
return(false);
}
pbw = pb;
wds[0].entryLength = Ethhdrsz + AppleDataSz;
wds[0].entryPtr = (Ptr) &LBPW;
wds[1].entryLength = 0;
LBPW.Destination = *enetaddr;
LBPW.Source = *enetaddr;
LBPW.EProtocoltype = 0x809B;
BlockMove((Ptr)AppleData,LBPW.testdata,AppleDataSz);
pbw.ecall.EWdsPointer = (Ptr) wds;
pbw.ctl.csCode = EWrite;
if (PBControl((ParmBlkPtr) &pbw,false)) /* write a packet to ourself */
{
killtest(&pbw,&pb);
return(false);
}
GetDateTime(&secs1);
while (pb.ctl.ioResult == 1) /* wait for default read to complete or timeout */
{
GetDateTime(&secs2);
if (secs2 - secs1 > 3)
{
killtest(&pbw,&pb);
return(false);
}
}
pbw.ctl.csCode = EDetachPH;
PBControl((ParmBlkPtr) &pbw,false);
if (!cmpdata(LBPR.testdata,LBPW.testdata,AppleDataSz)) /* check data looped back */
return(false);
return(true);
}

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/*
File: MACEecfg.r
Contains: 'ecfg' resource templates for MACE built-in ethernet systems
Written by: Mark A. Law
Copyright: © 1992-1993 by Apple Computer, Inc., all rights reserved.
Change History (most recent first):
<1> 6/7/93 kc first checked in
<LW2> 3/21/93 mal Versioned MACE 'ecfg' rsrc record and removed 24-bit MACEBase
field.
To Do:
*/
Type 'ecfg'
{
unsigned integer; /* Record version */
unsigned hex longint; /* 32-bit MACE address */
unsigned hex longint; /* Ethernet PROM address */
unsigned hex byte; /* MACE transmit frame control */
unsigned hex byte; /* MACE receive frame control */
unsigned hex byte; /* MACE xmit/recv fifo config control */
unsigned hex byte; /* MACE MAC config control */
hex string [6]; /* Alternate ethernet address */
unsigned integer; /* Alternate # transmit buffers */
unsigned integer; /* Alternate # receive buffers */
unsigned integer; /* Alternate # receive chains */
};
Resource 'ecfg' (43, "Cyclone33") {
1,
0x50F1C000,
0x50F08000,
0x1,
0,
0x2C,
0x3,
$"",
0,
0,
0
};
Resource 'ecfg' (78, "Cyclone40") {
1,
0x50F1C000,
0x50F08000,
0x1,
0,
0x2C,
0x3,
$"",
0,
0,
0
};
Resource 'ecfg' (60, "Tempest25") {
1,
0x50F1C000,
0x50F08000,
0x1,
0,
0x2C,
0x3,
$"",
0,
0,
0
};
Resource 'ecfg' (79, "Tempest33") {
1,
0x50F1C000,
0x50F08000,
0x1,
0,
0x2C,
0x3,
$"",
0,
0,
0
};

2729
DeclData/DeclNet/Mace/Mace.a Normal file

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#
# File Mace.Make
#
# Contains: Makefile for Mace.
#
# Written by: Kurt Clark, Chas Spillar, and Tim Nichols
#
# Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved.
#
# Change History (most recent first):
#
# <SM2> 6/14/93 kc Roll in Ludwig.
# <LW3> 3/16/93 chp Added a dependency on SysPrivateEqu.a for Mace.a.o.
# <LW2> 1/27/93 mal Add MACE ecfg rsrc.
# <SM2> 11/30/92 SWC Changed TimeEqu.a->Timer.a.
#
"{RsrcDir}DeclDataMace.rsrc" Ä "{ObjDir}MaceEnet.a.o" ¶
"{ObjDir}Mace.a.o" ¶
"{ObjDir}Loopback.c.o" ¶
"{IfObjDir}interface.o"
Link {StdLOpts} {StdAlign} -rt decl=1 -o "{Targ}" ¶
"{ObjDir}MaceEnet.a.o" ¶
"{ObjDir}Mace.a.o" ¶
"{ObjDir}Loopback.c.o" ¶
"{IfObjDir}interface.o"
"{RsrcDir}MACEecfg.rsrc" Ä {MaceDir}MACEecfg.r
Rez {StdROpts} -t rsrc -c RSED "{MaceDir}MACEecfg.r" -o "{Targ}"
"{ObjDir}Enet61.rsrc" Ä "{ObjDir}MaceEnet.a.o" ¶
"{ObjDir}Mace.a.o" ¶
"{ObjDir}Loopback.c.o"
Link {StdLOpts} {StdAlign} -rt enet=61 -o "{Targ}" ¶
-sn Main="Cyclone MACE Ethernet Driver" ¶
-ra "Cyclone MACE Ethernet Driver"=resSysHeap,resPurgeable,resLocked ¶
"{ObjDir}MaceEnet.a.o" ¶
"{ObjDir}Mace.a.o" ¶
"{ObjDir}Loopback.c.o" ¶
"{IfObjDir}interface.o"
"{ObjDir}MaceEnet.a.o" Ä "{MaceDir}MaceEnet.a" ¶
"{MaceDir}MaceEqu.a" ¶
"{MaceDir}VersionMaceEnet.a" ¶
"{EthernetDir}AtalkMacros.a" ¶
"{EthernetDir}ENETEqu.a" ¶
"{EthernetDir}SNMPLAP.a" ¶
"{AIncludes}GestaltEqu.a" ¶
"{AIncludes}Slots.a" ¶
"{AIncludes}SysEqu.a" ¶
"{AIncludes}SysErr.a" ¶
"{AIncludes}Timer.a" ¶
"{AIncludes}Traps.a" ¶
"{IntAIncludes}HardwarePrivateEqu.a"¶
"{IntAIncludes}InternalOnlyEqu.a" ¶
"{IntAIncludes}PSCEqu.a" ¶
"{IntAIncludes}UniversalEqu.a"
Asm {StdAOpts} -i "{MaceDir}" -i "{EthernetDir}" -o "{Targ}" "{MaceDir}MaceEnet.a"
"{ObjDir}Mace.a.o" Ä "{MaceDir}Mace.a" ¶
"{MaceDir}MaceEqu.a" ¶
"{EthernetDir}AtalkMacros.a" ¶
"{EthernetDir}ENETEqu.a" ¶
"{EthernetDir}SNMPLAP.a" ¶
"{AIncludes}GestaltEqu.a" ¶
"{AIncludes}SysEqu.a" ¶
"{AIncludes}SysErr.a" ¶
"{AIncludes}Traps.a" ¶
"{IntAIncludes}SysPrivateEqu.a" ¶
"{IntAIncludes}HardwarePrivateEqu.a"¶
"{IntAIncludes}InternalOnlyEqu.a" ¶
"{IntAIncludes}PSCEqu.a" ¶
"{IntAIncludes}UniversalEqu.a"
Asm {StdAOpts} -i "{MaceDir}" -i "{EthernetDir}" -o "{Targ}" "{MaceDir}Mace.a"

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;
; File: MaceEqu.a
;
; Contains: Equates for accessing the Ethernet Media Access
; Controller (MACE)
;
; Written by: Mark A. Law
;
; Copyright: © 1991-1993 by Apple Computer, Inc. All rights reserved.
;
; This file is used in these builds: Mac32
;
; Change History (most recent first):
;
; <SM6> 6/14/93 kc Roll in Ludwig.
; <LW4> 5/1/93 mal #1082434 Added records for new GetMem & FreeMem rtns.
; <LW3> 3/21/93 mal Versioned record for MACE 'ecfg' rsrc.
; <LW2> 1/27/93 mal Added MACEecfg rsrc support.
; <SM5> 12/4/92 mal Removed OFLO bit from recv pkt status.
; <SM4> 11/19/92 mal Added equ for yet another bit AMD didn't tell us about.
; <SM3> 10/30/92 mal MaceInitParms record change.
; <SM2> 10/13/92 mal -changed status thats passed to RecvRtn to lw
; <1> 10/6/92 GDW New location for ROMLink tool.
; <SM2> 6/22/92 mal Changes to support PSC2's (EVT2) Ethernet DMA receive model.
; <P4> 4/30/92 mal Expanded MaceInitParms record.
; <P3> 4/27/92 mal Added MaceInit parameters record.
; <P2> 3/23/92 mal Added MACE MAC config reg bit defines
;
; ---------------------------------------------------------
; MACE Registers
; ---------------------------------------------------------
MACERegBase EQU $50F1C000 ; Mace Reg Base on Cyclone
MACERegs RECORD 0
MACE_RX_FIFO DS.W 1 ;RD RXData -Read Status first
ORG *+$e
MACE_XMIT_FIFO DS.W 1 ;TX TXData
ORG *+$e
MACE_TX_FRM_CNTRL DS.B 1 ;RD/WR 01=Retry,XMTFCS,AUTOPAD
ORG *+$f
MACE_TX_FRM_STAT DS.B 1 ;RD
ORG *+$f
MACE_TX_RETRY_CNT DS.B 1 ;RD
ORG *+$f
MACE_RX_FRM_CNTRL DS.B 1 ;RD/WR 00 = Not_AutoStripPad
ORG *+$f
MACE_RX_FRM_STAT DS.B 1 ;RD Read 4x to get RX Status of packet
ORG *+$f
MACE_FIFO_FRM_CNT DS.B 1 ;RD Number of frames in FIFO
ORG *+$f
MACE_INT DS.B 1 ;RD_1 Interupt Source bits
ORG *+$f
MACE_INT_MSK DS.B 1 ;RD/WR Interupt Enables
ORG *+$f
MACE_POLL DS.B 1 ;RD Yet another status location
ORG *+$f
MACE_BIU_CNFG DS.B 1 ;RD/WR 20 = normal mode 01 = Soft Reset
ORG *+$f
MACE_FIFO_CNFG DS.B 1
ORG *+$f
MACE_MAC_CNFG DS.B 1 ;Enables
ORG *+$f
MACE_PLS_CNFG DS.B 1 ;RD/WR 0=Normal Mode
ORG *+$f
MACE_PHY_CNFG DS.B 1 ;RD/WR Reserved,Dude.
ORG *+$f
MACE_CHIP_ID_LOW DS.B 1 ;RD Just Reads ID
ORG *+$f
MACE_CHIP_ID_HIGH DS.B 1 ;RD Just Reads ID
ORG *+$f
MACE_ADDR_CNFG DS.B 1 ;RD/WR 04=Phy_Addr, 02=Log_Addr
ORG *+$1f
MACE_LOG_ADDR DS.B 1 ;Load with 6 Zeros
ORG *+$f
MACE_PHY_ADDR DS.B 1 ;Load with Address
ORG *+$2f
MACE_MISSED_PKT_CNT DS.B 1 ;RD
ORG *+$4f
MACE_USER_TEST_REG DS.B 1 ;
ENDR
;
; MACE Interrupt Reg. & Int. Reg. Mask Bit defines
; MACE Int. Reg - Read/Clear; MACE Int. Mask Reg. - Read/Write
;
BABL EQU 6 ; Babble, Xmit timeout error
CERR EQU 5 ; Signal Quality Error (SQE), xmit
RCVCO EQU 4 ; Receive Collision Cnt Overflow
MPCO EQU 2 ; Missed Pkt Cnt Overflow
RCVINT EQU 1 ; Rcv int
XMTINT EQU 0 ; Xmit int
; mask to disable all MACE ints
MaceIntMask EQU (1<<BABL)+(1<<CERR)+(1<<RCVCO)+(1<<MPCO)+(1<<RCVINT)+(1<<XMTINT)
OurIntsMask EQU (1<<RCVINT) ; ignore recv ints
;
; MACE Transmit Frame Status Reg. Bit defines
; Note: ONE and MORE are swapped prior to CURIO B0 MACE
;
XMTSV EQU 7 ; transmit status field valid when 1
UFLO EQU 6 ; underflow - xmit fifo
LCOL EQU 5 ; late collision
MORE EQU 4 ; more than 1 retry needed to xmit
ONE EQU 3 ; exactly 1 retry needed to xmit
DEFER EQU 2 ; transmission defered at least once
LCAR EQU 1 ; loss of carrier
RTRY EQU 0 ; retry
;
; MACE Transmit Frame Control Reg. Bit defines (byte)
;
DRTRY EQU 7 ; disable retry
DXMTFCS EQU 3 ; disable xmit fcs
APADXMT EQU 0 ; enable xmt autopad
; -forces generation of fcs
;
; MACE Receive Frame Control Reg. Bit defines (byte)
;
ASTRIPRCV EQU 0 ; enable rcv autopad stripping
; -forces stripping of fcs
;
; MACE Receive Status Reg. Bit defines (long)
;
; Receive Message Byte Count (byte0)
; Bits 7-0 : Recv Message Byte Count bits 7-0
; Receive Status (byte1)
; Bits 3-0 : Recv Message Byte Count bits 11-8
; Bits 7-4 : Recv Message Status bits
RcvOFLO EQU 7 ; receive fifo overflow
RcvCLSN EQU 6 ; late collision during recv
RcvFRAM EQU 5 ; frame error, non-integer # of bytes
RcvFCS EQU 4 ; frame check sequence error
; Receive Runt Packet Count (byte2)
; -number of runts recv'd since last successfully recv'd pkt
; -maxs at 255
; Receive Collision Count (byte3)
; -number of collisions since last successfully recv'd pkt
; -maxs at 255
;
; MACE Bus Interface Unit Reg. Bit defines (byte)
;
BSWAP EQU 7 ; byte swap mode, 0-Intel, 1-Motorola
; Transmit start point Bits 5-4
XMSTP EQU 4 ; bit shift offset
MACERESET EQU 0 ; software reset
; Transmit start point equates
; -controls when preamble xmit starts
XMTS4 EQU $00 ; start when 4 bytes in FIFO
XMTS16 EQU $10 ; start when 16 bytes in FIFO
XMTS64 EQU $20 ; start when 64 bytes in FIFO
XMTS112 EQU $30 ; start when 112 bytes in FIFO
;
; MACE FIFO Configuration Reg. Bit defines (byte)
; -fifo water mark changes ignored until fw reset bit set
; Transmit FIFO water mark Bits 7-6
XMTFW EQU 6 ; bit shift offset
; Receive FIFO water mark Bits 5-4
RCVFW EQU 4 ; bit shift offset
XMTFWR EQU 3 ; xmit fifo water mark reset
RCVFWR EQU 2 ; recv fifo water mark reset
XMTBRST EQU 1 ; xmit burst
RCVBRST EQU 0 ; recv burst
; FIFO watermark equates
RFW16 EQU $00 ; 16 byte recv FIFO watermark
RFW32 EQU $10 ; 32 byte recv FIFO watermark
RFW64 EQU $20 ; 64 byte recv FIFO watermark
TFW16 EQU $00 ; 16 byte xmit FIFO watermark
TFW32 EQU $40 ; 32 byte xmit FIFO watermark
TFW64 EQU $80 ; 64 byte xmit FIFO watermark
;
; MACE MAC Configuration Reg. Bit defines (byte)
;
PROMISC EQU 7 ; promiscuous mode, recv all valid frames
DXMT2PD EQU 6 ; disable xmit 2-part deferral algorithm
EMBA EQU 5 ; enable modified back-off algorithm
ENXMT EQU 1 ; enable xmit
ENRCV EQU 0 ; enable recv
;
; MACE Physical Layer Signaling Reg. Bit defines (byte)
;
XMTSEL EQU 3 ; xmit mode select
; Port Select Bits 2-1
PORTSEL EQU 1 ; bit shift offset
ENSTS EQU 0 ; enable optional I/O function status
;
; MACE Internal Address Configuration Reg. Bit defines (byte)
;
ADDRCHG EQU 7 ; address change enable
PHYADDR EQU 2 ; physical address select
LOGADDR EQU 1 ; logical address select
;
; MACE User Test Reg. Bit defines (byte)
;
;¥¥¥¥¥ WARNING: DO NOT EVER SET BIT 7 or you'll fry the MACE!!!! ¥¥¥¥¥
; Bit 6 (disable) is set during MACE init to disallow an erroneous and/or
; malicious setting of RTRE.
RTRE EQU 7 ; reserved test register enable
RTRD EQU 6 ; reserved test register disable
;¥¥¥¥¥
RPA EQU 5 ; runt packet accept
FCOLL EQU 4 ; force a collision, use with loopback
RCVFCSE EQU 3 ; receive fcs enable, use with loopback
; Loopback control Bits 2-1, %XX0 ¥¥¥ NOT FOR BIT SHIFTS!
NOLPB EQU %000 ; disable loopback mode
EXTLPB EQU %010 ; external loopback mode
INTLPB EQU %100 ; internal loopback, no MENDEC
MENDECLPB EQU %110 ; internal loopback, with MENDEC
;
; Misc. equates
;
MondoPkt EQU 2000 ; Value > max pkt, used for Recv DMA cnt
CntRegMask EQU $0001ffff ; Ignore upper 15 bits
nobuff EQU -2 ; no xmit buffer available
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Network Statistics
NetStats RECORD 0 ; network management stats.
TxOK DS.L 1 ; frames transmitted OK
sCollFrame DS.L 1 ; single collision frames
mCollFrame DS.L 1 ; multiple collision frames
CollFrame DS.L 1 ; collision frames
DefTx DS.L 1 ; deferred transmissions
LateColl DS.L 1 ; late collisions
ExcessColl DS.L 1 ; excessive collisions
ExcessDef DS.L 1 ; excessive defferals
InMACTxErr DS.L 1 ; internal MAC transmit errors
RxOK DS.L 1 ; frames received OK
MultiRxOK DS.L 1 ; multicast frames recd OK
BroadRxOK DS.L 1 ; broadcast frames recd OK
FCSerr DS.L 1 ; frame check sequence errors
FAerr DS.L 1 ; frame alignment errors
MPerr DS.L 1 ; missed packet errors
Size EQU *
ENDR
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ General Equates
TalliesPerSec EQU 5000000 ; number of timer ticks/second
TxMaxRetries EQU 4 ; max attempts to retry aborted xmits
Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets
Min_Pkt_Size EQU 60 ; minimum packet size
Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers
Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC)
EOL_Bit EQU 0 ; end-of-link bit
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ For GetMemory call
GetMem RECORD 0
memsize DS.l 1 ; requested size
memoptions DS.l 1 ; requested options
memhndl DS.l 1 ; handle to memory mgr block
memhndla DS.l 1 ; handle to 4 or 8k aligned memory
memhndlasz DS.l 1 ; ptr to 4 or 8k aligned memory size
GetMemSz EQU *
ENDR
Locked EQU 0 ; want locked memory
Contig EQU 1 ; want contiguous memory
CacheOff EQU 2 ; want non-cacheable memory
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ For FreeMemory call
FreeMem RECORD 0
memoptions DS.l 1 ; requested options
memptr DS.l 1 ; ptr to memory mgr block
memptra DS.l 1 ; ptr to 4 or 8k aligned memory
memptrasz DS.l 1 ; 4 or 8k aligned memory size
FreeMemSz EQU *
ENDR
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Initialization Parameters
MACEInitParms RECORD 0
RecvRtn DS.l 1 ; address of Ethernet receive routine
RecvPrms DS.l 1 ; parms to pass @ receive
XmitRtn DS.l 1 ; address of Ethernet xmit complete routine
XmitPrms DS.l 1 ; parms to pass @ xmit complete
MACECfgPtr DS.l 1 ; ptr to MACE config record
Dot3NetStats DS.l 1 ; ptr to 802.3 statistics array
LAPMIBNetStats DS.l 1 ; ptr to LAP MIB statistics array
EnetAddr DS.l 1 ; ptr to ethernet address
FastMoveRtn DS.l 1 ; ->proc to move memory FAST
IPSize EQU *
ENDR
;¥¥¥¥ Parms passed to .ENET "RecvRtn"
RcvParms RECORD {A6Link}
Size EQU * ; no local vars
A6Link DS.l 2 ; saved A6 and return addr
Parm DS.l 1 ; parm passed to MaceInit
Buff DS.l 1 ; ptr to Mace's buffer containing pkt
Pkt DS.l 1 ; ptr to packet data
Len DS.w 1 ; pkt length
Stat DS.l 1 ; pkt status
; Stat definition:
; Byte 0: Receive Runt Packet Count (Bits 31-24)
; -number of runts recv'd since last successfully recv'd pkt
; -maxs at 255
; Byte 1: Receive Collision Count (Bits 23-16)
; -number of collisions since last successfully recv'd pkt
; -maxs at 255
; Byte 2-3: Receive Status (Bits 15-0)
; Bits 15-7,3-0 : reserved, read as 0's
; Bits 6-4 : Recv Message Status bits
; RcvCLSN EQU 6 ; late collision during recv
; RcvFRAM EQU 5 ; frame error, non-integer # of bytes
; RcvFCS EQU 4 ; frame check sequence error
ParmsSz EQU * - Parm ; len of passed parms
ENDR
Configrsrc EQU 'ecfg' ; rsrc type for MACE config data rsrc
; Mace Configuration Record
MACECfg RECORD 0 ; Config values from config rsrc
MACECfgVers DS.w 1 ; record version
MACEBase DS.l 1 ; Base address of MACE
EnetPROM DS.l 1 ; base address of Address Prom
XmitFrmCtl DS.b 1 ; MACE transmit frame control register value
RecvFrmCtl DS.b 1 ; MACE receive frame control register value
FIFOCfgCtl DS.b 1 ; MACE xmit/recv fifo config control register value
MACCfgCtl DS.b 1 ; MACE MAC config control register value
; The following are optional values; ignored if zero
EnetAddr DS.b 6 ; Alternate Ethernet Address, overrides Address PROM
XmitBuffs DS.w 1 ; Alternate number of transmit buffers
RecvBuffs DS.w 1 ; Alternate number of receive buffers
RecvChains DS.w 1 ; Alternate number of receive "chains"
CfgSize EQU *
ENDR

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# Contains: Makefile for PDM MACE Ethernet driver.
#
# Written by: Dave Calvert
#
# Copyright: © 1993 by Apple Computer, Inc., all rights reserved.
#
# Change History (most recent first):
#
# <SM6> 3/5/93 dwc Changed DeclDataPDMMace.rsrc ID to be unique from
# DeclDataMace.rsrc.
# <SM3> 3/4/93 dwc Added DeclDataPDMMace definition for PDM ENET.
# <SM2> 2/25/93 dwc Re-enable loopbacktests and include Interface.o for them.
# <SM2> 2/4/93 RC Took out Loopback.c.o link and fixed {make} to {makedir}
#
#===============================================================================
# Create DeclData Resource for PDM Declaration ROM
#===============================================================================
"{RsrcDir}DeclDataPDMMace.rsrc" Ä "{ObjDir}PDMMaceEnet.a.o" ¶
"{ObjDir}PDMMace.a.o" ¶
"{ObjDir}Loopback.c.o" ¶
"{IfObjDir}interface.o"
Link {StdLOpts} {StdAlign} -rt decl=1 -o "{Targ}" ¶
"{ObjDir}PDMMaceEnet.a.o" ¶
"{ObjDir}PDMMace.a.o" ¶
"{ObjDir}Loopback.c.o" ¶
"{IfObjDir}Interface.o"
"{RsrcDir}PDMENET.rsrc" Ä "{ObjDir}PDMMaceEnet.a.o" ¶
"{ObjDir}PDMMace.a.o" ¶
"{PDMMaceDir}PDMEnet.make" ¶
"{ObjDir}Loopback.c.o" ¶
"{IfObjDir}Interface.o"
Link -t rsrc -c RSED -sn Main="PDM MACE Ethernet Driver" ¶
-ra "PDM MACE Ethernet Driver"=resSysHeap,resPurgeable,resLocked ¶
-rt enet=57 -o {Targ} ¶
"{ObjDir}PDMMaceEnet.a.o" ¶
"{ObjDir}PDMMace.a.o" ¶
"{ObjDir}Loopback.c.o" ¶
"{IfObjDir}Interface.o"
"{RsrcDir}PDMENET57.rsrc" Ä "{ObjDir}PDMMaceEnet.a.o" ¶
"{ObjDir}PDMMace.a.o" ¶
# "{ObjDir}Loopback.c.o" ¶
"{PDMMaceDir}PDMEnet.make"
Link -t rsrc -c RSED -sn Main="PDM MACE Ethernet Driver" ¶
-ra "PDMENET"=resSysHeap,resPurgeable,resLocked ¶
-rt enet=57 -o {Targ} ¶
"{ObjDir}PDMMaceEnet.a.o" ¶
# "{ObjDir}Loopback.c.o" ¶
"{ObjDir}PDMMace.a.o"
#===============================================================================
# Assemble Stuff
#===============================================================================
"{ObjDir}PDMMace.a.o" Ä "{PDMMaceDir}PDMMace.a" ¶
"{PDMMaceDir}PDMMaceEqu.a" ¶
"{IntAIncludes}AMICEqu.a" ¶
"{IntAIncludes}UniversalEqu.a" ¶
"{EthernetDir}ATalkMacros.a" ¶
"{PDMMaceDir}PDMEnet.make"
Asm {StdAOpts} {Defs} -i "{PDMMaceDir}" -i "{EthernetDir}" -o "{Targ}" "{PDMMaceDir}PDMMace.a"
"{ObjDir}PDMMaceEnet.a.o" Ä "{PDMMaceDir}PDMMaceEnet.a" ¶
"{PDMMaceDir}PDMMaceEqu.a" ¶
"{PDMMaceDir}VersionPDMMaceEnet.a" ¶
"{EthernetDir}802Equ.a" ¶
"{EthernetDir}ATalkMacros.a" ¶
"{EthernetDir}ENETEqu.a" ¶
"{EthernetDir}SNMPLAP.a" ¶
"{IntAIncludes}UniversalEqu.a" ¶
"{IntAIncludes}AMICEqu.a" ¶
"{AIncludes}GestaltEqu.a" ¶
"{AIncludes}SysEqu.a" ¶
"{AIncludes}SysErr.a" ¶
"{AIncludes}Traps.a" ¶
"{AIncludes}Slots.a" ¶
"{PDMMaceDir}PDMEnet.make"
Asm {StdAOpts} {Defs} -i "{PDMMaceDir}" -i "{EthernetDir}" -o "{Targ}" "{PDMMaceDir}PDMMaceEnet.a"

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;
; File: PDMMaceEqu.a
;
; Contains: Equates for accessing the Ethernet Media Access
; Controller (MACE) for the PDM ENET driver
;
; Written by: Dave Calvert
;
; Copyright: © 1992-1993 by Apple Computer, Inc. All rights reserved.
;
; This file is used in these builds: ROM RISC (PDM ENET)
;
; Change History (most recent first):
;
; <SM10> 6/2/93 GMR Changed some of the init parameters (back to Mark's equates),
; modified the receive record/status definitions.
; <SM9> 5/27/93 dwc Added support for AMIC work-around code.
; <SM8> 5/25/93 dwc Clean up for Alpha.
; <SM7> 5/4/93 dwc Added debug code to work around AMIC's returning FF's on the
; first read.
; <SM6> 4/6/93 dwc Added status/packet logging equate.
; <SM5> 3/24/93 dwc Remove obsolete code and added code to try to recover from
; lowered interrupt level during packet handling.
; <SM4> 3/5/93 dwc Removed some more debugging code.
; <SM3> 2/25/93 dwc Enable receive, remove some debug equates.
; <SM2> 2/24/93 dwc Cleaned up some debug equates, added some more debug equates,
; disabled receive for the PDM D5 ROM build.
; <SM1> 2/4/93 dwc first checked in
;
;
; ---------------------------------------------------------
; MACE Registers
; ---------------------------------------------------------
MACERegBase EQU $50F1C000 ; Mace Reg Base on Cyclone
MACERegs RECORD 0
MACE_RX_FIFO DS.W 1 ;RD RXData -Read Status first
ORG *+$e
MACE_XMIT_FIFO DS.W 1 ;TX TXData
ORG *+$e
MACE_TX_FRM_CNTRL DS.B 1 ;RD/WR 01=Retry,XMTFCS,AUTOPAD
ORG *+$f
MACE_TX_FRM_STAT DS.B 1 ;RD
ORG *+$f
MACE_TX_RETRY_CNT DS.B 1 ;RD
ORG *+$f
MACE_RX_FRM_CNTRL DS.B 1 ;RD/WR 00 = Not_AutoStripPad
ORG *+$f
MACE_RX_FRM_STAT DS.B 1 ;RD Read 4x to get RX Status of packet
ORG *+$f
MACE_FIFO_FRM_CNT DS.B 1 ;RD Number of frames in FIFO
ORG *+$f
MACE_INT DS.B 1 ;RD_1 Interupt Source bits
ORG *+$f
MACE_INT_MSK DS.B 1 ;RD/WR Interupt Enables
ORG *+$f
MACE_POLL DS.B 1 ;RD Yet another status location
ORG *+$f
MACE_BIU_CNFG DS.B 1 ;RD/WR 20 = normal mode 01 = Soft Reset
ORG *+$f
MACE_FIFO_CNFG DS.B 1
ORG *+$f
MACE_MAC_CNFG DS.B 1 ;Enables
ORG *+$f
MACE_PLS_CNFG DS.B 1 ;RD/WR 0=Normal Mode
ORG *+$f
MACE_PHY_CNFG DS.B 1 ;RD/WR Reserved,Dude.
ORG *+$f
MACE_CHIP_ID_LOW DS.B 1 ;RD Just Reads ID
ORG *+$f
MACE_CHIP_ID_HIGH DS.B 1 ;RD Just Reads ID
ORG *+$f
MACE_ADDR_CNFG DS.B 1 ;RD/WR 04=Phy_Addr, 02=Log_Addr
ORG *+$1f
MACE_LOG_ADDR DS.B 1 ;Load with 6 Zeros
ORG *+$f
MACE_PHY_ADDR DS.B 1 ;Load with Address
ORG *+$2f
MACE_MISSED_PKT_CNT DS.B 1 ;RD
ORG *+$4f
MACE_USER_TEST_REG DS.B 1 ;
ENDR
;
; MACE Interrupt Reg. & Int. Reg. Mask Bit defines
; MACE Int. Reg - Read/Clear; MACE Int. Mask Reg. - Read/Write
;
BABL EQU 6 ; Babble, Xmit timeout error
CERR EQU 5 ; Signal Quality Error (SQE), xmit
RCVCO EQU 4 ; Receive Collision Cnt Overflow
MPCO EQU 2 ; Missed Pkt Cnt Overflow
RCVINT EQU 1 ; Rcv int
XMTINT EQU 0 ; Xmit int
; mask to disable all MACE ints
;
; MACE Poll register bits
;
TDTREQ EQU 6 ; Transmit data request
RTDREQ EQU 5 ; Receive data request
;==========================================================================================
; _SETTHEINTMASK
;
; Macro for setting the interrupt level to an arbitrary level. Pass the level in
; a Data register.
;==========================================================================================
MACRO
_SETTHEINTMASK &sReg
move.w SR,-(SP)
or.w &sReg,(SP)
move.w (SP)+,SR
ENDM
MaceIntMask EQU (1<<BABL)+(1<<CERR)+(1<<RCVCO)+(1<<MPCO)+(1<<RCVINT)+(1<<XMTINT)
OurIntsMask EQU (1<<RCVINT) ; Ignore only these interrupts from MACE
;
; MACE Transmit Frame Status Reg. Bit defines
; Note: ONE and MORE are swapped prior to CURIO B0 MACE
;
XMTSV EQU 7 ; transmit status field valid when 1
UFLO EQU 6 ; underflow - xmit fifo
LCOL EQU 5 ; late collision
MORE EQU 4 ; more than 1 retry needed to xmit
ONE EQU 3 ; exactly 1 retry needed to xmit
DEFER EQU 2 ; transmission defered at least once
LCAR EQU 1 ; loss of carrier
RTRY EQU 0 ; retry
;
; MACE Transmit Frame Control Reg. Bit defines (byte)
;
DRTRY EQU 7 ; disable retry
DXMTFCS EQU 3 ; disable xmit fcs
APADXMT EQU 0 ; enable xmt autopad
; -forces generation of fcs
;
; MACE Receive Frame Control Reg. Bit defines (byte)
;
ASTRIPRCV EQU 0 ; enable rcv autopad stripping
; -forces stripping of fcs
;
; MACE Receive Status Reg. Bit defines (long)
;
; Receive Message Byte Count (byte0)
; Bits 7-0 : Recv Message Byte Count bits 7-0
; Receive Status (byte1)
; Bits 3-0 : Recv Message Byte Count bits 11-8
; Bits 7-4 : Recv Message Status bits
RcvOFLO EQU 7 ; receive fifo overflow
RcvCLSN EQU 6 ; late collision during recv
RcvFRAM EQU 5 ; frame error, non-integer # of bytes
RcvFCS EQU 4 ; frame check sequence error
; Receive Runt Packet Count (byte2)
; -number of runts recv'd since last successfully recv'd pkt
; -maxs at 255
; Receive Collision Count (byte3)
; -number of collisions since last successfully recv'd pkt
; -maxs at 255
;
; MACE Bus Interface Unit Reg. Bit defines (byte)
;
BSWAP EQU 7 ; byte swap mode, 0-Intel, 1-Motorola
; Transmit start point Bits 5-4
XMSTP EQU 4 ; bit shift offset
MACERESET EQU 0 ; software reset
; Transmit start point equates
; -controls when preamble xmit starts
XMTS4 EQU $00 ; start when 4 bytes in FIFO
XMTS16 EQU $10 ; start when 16 bytes in FIFO
XMTS64 EQU $20 ; start when 64 bytes in FIFO
XMTS112 EQU $30 ; start when 112 bytes in FIFO
;
; MACE FIFO Configuration Reg. Bit defines (byte)
; -fifo water mark changes ignored until fw reset bit set
; Transmit FIFO water mark Bits 7-6
XMTFW EQU 6 ; bit shift offset
; Receive FIFO water mark Bits 5-4
RCVFW EQU 4 ; bit shift offset
XMTFWR EQU 3 ; xmit fifo water mark reset
RCVFWR EQU 2 ; recv fifo water mark reset
XMTBRST EQU 1 ; xmit burst
RCVBRST EQU 0 ; recv burst
; FIFO watermark equates
RFW16 EQU $00 ; 16 byte recv FIFO watermark
RFW32 EQU $10 ; 32 byte recv FIFO watermark
RFW64 EQU $20 ; 64 byte recv FIFO watermark
TFW16 EQU $00 ; 16 byte xmit FIFO watermark
TFW32 EQU $40 ; 32 byte xmit FIFO watermark
TFW64 EQU $80 ; 64 byte xmit FIFO watermark
;
; MACE MAC Configuration Reg. Bit defines (byte)
;
PROMISC EQU 7 ; promiscuous mode, recv all valid frames
DXMT2PD EQU 6 ; disable xmit 2-part deferral algorithm
EMBA EQU 5 ; enable modified back-off algorithm
ENXMT EQU 1 ; enable xmit
ENRCV EQU 0 ; enable recv
;
; MACE Physical Layer Signaling Reg. Bit defines (byte)
;
XMTSEL EQU 3 ; xmit mode select
; Port Select Bits 2-1
PORTSEL EQU 1 ; bit shift offset
ENSTS EQU 0 ; enable optional I/O function status
;
; MACE Internal Address Configuration Reg. Bit defines (byte)
;
ADDRCHG EQU 7 ; address change enable
PHYADDR EQU 2 ; physical address select
LOGADDR EQU 1 ; logical address select
;
; MACE User Test Reg. Bit defines (byte)
;
;¥¥¥¥¥ WARNING: DO NOT EVER SET BIT 7 or you'll fry the MACE!!!! ¥¥¥¥¥
; Bit 6 (disable) is set during MACE init to disallow an erroneous and/or
; malicious setting of RTRE.
RTRE EQU 7 ; reserved test register enable
RTRD EQU 6 ; reserved test register disable
;¥¥¥¥¥
RPA EQU 5 ; runt packet accept
FCOLL EQU 4 ; force a collision, use with loopback
RCVFCSE EQU 3 ; receive fcs enable, use with loopback
; Loopback control Bits 2-1, %XX0 ¥¥¥ NOT FOR BIT SHIFTS!
NOLPB EQU %000 ; disable loopback mode
EXTLPB EQU %010 ; external loopback mode
INTLPB EQU %100 ; internal loopback, no MENDEC
MENDECLPB EQU %110 ; internal loopback, with MENDEC
;
; Misc. equates
;
MondoPkt EQU 2000 ; Value > max pkt, used for Recv DMA cnt
AddrPROM EQU $50F08000 ; 32 bit address of address PROM
CntRegMask EQU $0001ffff ; Ignore upper 15 bits
nobuff EQU -2 ; no xmit buffer available
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Network Statistics
NetStats RECORD 0 ; network management stats.
TxOK DS.L 1 ; frames transmitted OK
sCollFrame DS.L 1 ; single collision frames
mCollFrame DS.L 1 ; multiple collision frames
CollFrame DS.L 1 ; collision frames
DefTx DS.L 1 ; deferred transmissions
LateColl DS.L 1 ; late collisions
ExcessColl DS.L 1 ; excessive collisions