;==========================================================================
;
;	File:		SCSIEqu53c96.a
;
;	Contains:	Equates for dealing with the SCSI 53c96 chip
;
;	Written by:	Jonathan Abilay/Paul Wolf
;
;	Copyright:	© 1990-1993 by Apple Computer, Inc., all rights reserved.
;
;	Change History (most recent first):
;
;	  <SM16>	10/14/93	pdw		<MC> roll-in.
;	   <MC3>	10/12/93	pdw		Added support for Synchronous data transfers, rewrote State
;									Machine, message handling etc.
;	   <MC2>	 9/16/93	pdw		Tailoring the Select timeout values for 20 and 40MHz clock
;									speeds to about 200mS instead of 250mS to see if anybody
;									complains.
;	  <SM15>	  9/9/93	pdw		Lots of little changes.  Name changes, temporary cache_bug
;									stuff.
;	  <SM14>	 7/17/93	pdw		Changed tc bit to bTermCnt (I think).
;	  <SM13>	 6/29/93	pdw		Massive checkins: Change asynchronicity mechanism to CallMachine
;									stack switching mechanism.  Adding support for Cold Fusion.
;									Rearranging HW/SW Init code. Some code optimizations.
;	  <SM12>	 5/25/93	DCB		Rollin from Ludwig. (The next item below)
;	   <LW5>	 5/21/93	PW		Adding target mode commands so that we can respond to a select
;									without toasting the bus.
;	  <SM11>	  5/5/93	PW		Converted names to meanies-friendly names.  Updated with latest
;									from Ludwig stuff.
;	   <LW3>	 3/26/93	PW		Removed initCFx values.
;	   <SM9>	 1/31/93	PW		Update from the latest of Ludwig. Also changes required for PDM
;									(will update Ludwig with these as needed myself).
;	   <LW2>	 1/27/93	PW		Once again, added mSCSIRstRptIntDis to CF1.
;	   <SM8>	 12/5/92	PW		Got rid of confusing and worthless iDcBsxx stuff.
;	   <SM7>	11/17/92	DCB		Changed initCF1: added mSCSIRstRptIntDis to disable interrupt on
;									reset until we figure out what's going on.
;	   <SM6>	11/12/92	PW		Rearranged a bit more logically and put 'm's in front of masks
;									and added some more stuff.  Removed parityEnable.
;	   <SM5>	10/30/92	DCB		Changed some flags for to support changes to the interrupt
;									handling routines
;	   <SM4>	 10/8/92	PW		Added bit definitions for status register.
;	   <SM3>	 8/31/92	PW		Added vowels.  Changed FFO to FIFO, Flsh to Flush, Rst to Reset,
;									S to SCSI, Chp to Chip, Acep to Accept, rFOS to rFIFOflags.
;	   <SM2>	 8/30/92	PW		Added cDMASelWAtn3 and cSelWAtn3 commands to equates.
;	   <SM1>	 -			PW		Initial check-in.
;
;==========================================================================

	IF &TYPE('__INCLUDING_SCSIEqu53c96__') = 'UNDEFINED' THEN
__INCLUDING_SCSIEqu53c96__	SET	1


;---------------------------------------------------
;  SCSI 53C96  Command Set
;---------------------------------------------------
;Note:
;	for NON-DMA mode, bit7=0.  DMA mode command bytes have bit7=1.

cNOP			EQU		$00		; NOP command
cFlushFIFO		EQU		$01		; flush FIFO command							<SM3> pdw
cResetChip		EQU		$02		; reset SCSI chip								<SM3> pdw
cResetSCSIBus	EQU		$03		; reset SCSI bus								<SM3> pdw

cIOXfer			EQU		$10		; non-DMA Transfer command
cCmdComplete	EQU		$11		; Initiator Command Complete Sequence			<SM3> pdw
cMsgAccept		EQU		$12		; Message Accepted								<SM3> pdw

cSendMsg		EQU		$20		; Send Message byte(s)
cSendStatus		EQU		$21		; Send status byte
cSendData		EQU		$22		; Send data byte(s)
cDisconnectSeq	EQU		$23		; Send 2 msg bytes and disconnect
cTerminateSeq	EQU		$24		; Send status byte, message byte then disconnect
cTgtCmdComplete	EQU		$25		; Send status byte, message byte DON'T disconnect
cDisconnect		EQU		$27		; Disconnect (drop busy)
cRcvMsgSeq		EQU		$28		; Receive Message byte(s)
cRcvCmd			EQU		$29		; Receive command byte(s) (specified count)
cRcvData		EQU		$2a		; Receive data byte(s)
cRcvCmdSeq		EQU		$29		; Receive command byte(s) (decoded count)
cStopDMA		EQU		$04		; stop DMA

cSelWOAtn		EQU		$41		; Select Without ATN Sequence
cSelWAtn		EQU		$42		; Select With ATN Sequence
cSelWAtnStop	EQU		$43		; Select With ATN and Stop Sequence				<SM3> pdw
cSelWAtn3		EQU		$46		; Select With ATN 3 (msg_out bytes) Sequence	<SM2> pdw

cEnableR_sel	EQU		$44		; Enable (re)selection

cSetAtn			EQU		$1A		; Set ATN command
cRstAtn			EQU		$1B		; Reset ATN command

cDMAXfer		EQU		$90		; DMA Transfer command
cDMASelWOAtn	EQU		$C1		; Select Without ATN Sequence, use DMA
cDMASelWAtn		EQU		$C2		; Select With ATN Sequence, use DMA
cDMASelWAtnStop	EQU		$C3		; Select With ATN and Stop Sequence				<SM3> pdw
cDMASelWAtn3	EQU		$C6		; Select With ATN 3 (msg_out bytes) Sequence	<SM2> pdw


;---------------------------------------------------
;  SCSI 53C96  Register Defs, Offsets
;---------------------------------------------------

nonSerlzdDisp	EQU		$040000		; disp. between serlzd and non-serlzd I/O images

rXCL		EQU		$00		; Transfer count bits 0-7 	(r/w)
rXCM		EQU		$10		; Transfer count bits 8-15	(r/w)
rFIFO		EQU		$20		; FIFO 						(r/w)
rCMD		EQU		$30		; Command 					(r/w)
rCF1		EQU		$80		; Configuration 1 			(w)
rCF2		EQU		$B0		; Configuration 2 			(w)
rCF3		EQU		$C0		; Configuration 3 			(w)

rSTA		EQU		$40		; Status 					(r)
rINT		EQU		$50		; Interrupt 				(r)
rSQS		EQU		$60		; Sequence Step 			(r)
rFIFOflags	EQU		$70		; FIFO Flags/Sequence Step 	(r)

rDID		EQU		$40		; Destination Bus ID 		(w)
rSTO		EQU		$50		; Select/Reselect Timeout 	(w)
rSyncPeriod	EQU		$60		; Synchronous Period 		(w)
rSyncOffset	EQU		$70		; Synchronous Offset 		(w)
rCKF		EQU		$90		; Clock Conversion Factor 	(w)
rTST		EQU		$A0		; Test 						(w)
rXCH		EQU		$E0		; Transfer count bits 16-24	(r/w)
rChipID		EQU		rXCH	; Chip ID register			(r)
rFIFObtm	EQU		$F0		; Reserve FIFO Byte 		(w)

rDMA		EQU		$100	; Pseudo-DMA regr		(r/w)


;ΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡ
;  SCSI 53C96  Bit Defs
;ΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡΡ

;ΡΡΡΡ Interrupt Register (rINT) bits ΡΡΡΡ
bSelected		EQU			0		; selected interrupt
bSelectedWAtn	EQU			1		; selected w/atn interrupt
bReselected		EQU			2		; reselected interrupt
bFuncComplete	EQU			3		; function complete bit	
bBusService		EQU			4		; bus service bit		
bDisconnected	EQU			5		; disconnected bit		
bIllegalCmd		EQU			6		; illegal command interrupt
bResetDetected	EQU			7		; SCSI reset detected interrupt

;ΙΙΙ masks ΙΙΙ
mSelected		EQU			1<<bSelected
mSelectedWAtn	EQU			1<<bSelectedWAtn
mReselected		EQU			1<<bReselected
mFuncComplete	EQU			1<<bFuncComplete
mBusService		EQU			1<<bBusService	
mDisconnected	EQU			1<<bDisconnected	
mIllegalCmd		EQU			1<<bIllegalCmd
mResetDetected	EQU			1<<bResetDetected

mNonNormalInt	EQU		mIllegalCmd + mReselected + mSelected + mSelectedWAtn + mResetDetected


;ΡΡΡΡ Status Register (rSTA) bits ΡΡΡΡ
bCmdXferComp	EQU			3		; Gross Error
bTermCount		EQU			4		; terminal count
bParityError	EQU			5		; Parity Error
bGrossError		EQU			6		; Gross Error
bINT			EQU			7		; interrupt

iPhaseMsk		EQU			$07		; MASK value for phase bits

;ΡΡΡΡ Command Register (rCMD) bits ΡΡΡΡ
bINTMode		EQU			4		; initiator mode command
bTRGMode		EQU			5		; target mode command
bDSCMode		EQU			6		; disconnected mode command

;ΡΡΡΡ Configuration 1 Register (rCF1) bits ΡΡΡΡ
mCF1_SlowCableMode		EQU		$80			; Slow Cable Mode enabled bit
mCF1_ResetIntrpDisable	EQU   	$40			; SCSI Reset Reporting Intrp Disabled bit	<SM7>
mCF1_ParityTestMode		EQU    	$20			; Parity Test Mode bit
mCF1_EnableParity		EQU    	$10			; Enable Parity Checking bit
mCF1_ChipTestMode		EQU    	$08			; Enable Chip Test Mode bit

mCF1_MyBusID			EQU    	$07			; My SCSI Bus ID Mask

;ΡΡΡΡ Configuration 2 Register (rCF2) bits ΡΡΡΡ
mCF2_ReserveFIFOByte	EQU		$80			; Reserve FIFO Byte
mCF2_FeaturesEnable		EQU   	$40			; Enable Phase Latch
											; 53F96: turns on 24bit xfer count also
mCF2_EnableByteControl	EQU    	$20			; Enable Byte Control
mCF2_DREQHiZ			EQU    	$10			; DREQ High Impedance

mCF2_SCSI2				EQU    	$08			; SCSI-2 Mode
mCF2_TgtBadParityAbort	EQU   	$04			; Target Bad Parity Abort
mCF2_RegisterParity		EQU    	$02			; Regr Parity Enable
mCF2_DMAParity			EQU    	$01			; DMA Parity Enable

;ΡΡΡΡ Configuration 3 Register (rCF3) bits ΡΡΡΡ
mCF3_FastSCSI			EQU		$10			; set if rate>5MB/s
mCF3_FastClock			EQU		$08			; set if clock = 40MHz
mCF3_SaveResidual		EQU		$04			; Save Residual Byte
mCF3_AltDMAMode			EQU		$02			; Alternate DMA Mode
mCF3_Threshold8			EQU		$01			; Threshold 8

;ΡΡΡΡ Other Register bits ΡΡΡΡ	
mSQSMsk					EQU		$07			; sequence bits mask value  (rSQS)
mFIFOCount				EQU		$1F			; FIFO count mask value		(rFOS)
mSyncOffset				EQU		$0F			; synchronous offset bits	(rSYO)
mSyncPeriod				EQU		$1F			; synchronous period bits	(rSYP)

;---------------------------------------------------
;  Miscellaneous Constants
;---------------------------------------------------

iFifoSize	EQU		$10		; FIFO size in bytes


;---------------------------------------------------
;  53c96 Register Values
;---------------------------------------------------

;ΡΡΡΡΡ Phase values (for iPhaseMsk bits in rSTA) ΡΡΡΡΡ
iDataOut	EQU		$00		; Data-Out SCSI Phase value
iDataIn		EQU		$01		; Data-In SCSI Phase value
iCommand	EQU		$02		; Command Phase value
iStatus		EQU		$03		; Status Phase value
iMsgOut		EQU		$06		; Msg-Out SCSI Phase value
iMsgIn		EQU		$07		; Msg-In SCSI Phase value


;ΡΡΡΡΡ Clock Conversion Values (based on SCSI chip clock - not CPU clock) ΡΡΡΡΡ
ccf10MHz				EQU		$02			; CLK conv factor 10.0Mhz
ccf11to15MHz			EQU    	$03			; CLK conv factor 10.01 to 15.0Mhz
ccf16to20MHz			EQU    	$04			; CLK conv factor 15.01 to 20.0Mhz
ccf21to25MHz			EQU    	$05			; CLK conv factor 20.01 to 25.0Mhz
ccf26to30MHz			EQU    	$06			; CLK conv factor 25.01 to 30.0Mhz
ccf31to35MHz			EQU    	$07			; CLK conv factor 30.01 to 35.0Mhz	
ccf36to40MHz			EQU    	$00			; CLK conv factor 35.01 to 40.0Mhz (0 := 8)

SelTO16Mhz				EQU		126			; ($7e)  using the formula: RV (regr value)		
											;   126 =  (16MHz * 250mS)/ (7682 * 4)			
											;    250mS is ANSI standard.
										
SelTO20Mhz				EQU		132;160	; ($)  using the formula: RV (regr value)		
											;   162 =  (20MHz * 250mS)/ (7682 * 4)			
											;    250mS is ANSI standard.
										
SelTO25Mhz				EQU		167			; ($a7)  using the formula: RV (regr value)
											;   163 =  (25MHz * 250mS)/ (7682 * 5)
											;    250mS is ANSI standard.

SelTO33Mhz				EQU		167			; ($a7)  using the formula: RV (regr value)		
											;   153 =  (33MHz * 250mS)/ (7682 * 7)
											;    250mS is ANSI standard.

SelTO40Mhz				EQU		132;160	; ($a7)  using the formula: RV (regr value)
											;   163 =  (40MHz * 250mS)/ (7682 * 8)
											;    250mS is ANSI standard.					

										; <SM5>

;ΡΡΡΡΡ Values to use ΡΡΡΡΡ
asyncXfer			EQU		$0			; Asynchronous Data Transfer = 0 Synch Offset value
										; 	a non-zero value indicates Synch data xfer
										
initOp				EQU		asyncXfer	; use this operation

;--------------------------------------------------- 
;  SCSI DAFB Register Information	
;--------------------------------------------------- 
 
SCSI0_DAFB		EQU		$F9800024		; DAFB address to access SCSI1 DREQ bit							
SCSI1_DAFB		EQU		$F9800028		; DAFB address to access SCSI2 DREQ bit							
bDREQ			EQU		9				; SCSI DREQ status bit											

tsc_cf_stg_25	EQU		$1EC			; DAFB state maching config value for 25 MHz CPU
tsc_cf_stg_33	EQU		$041			; DAFB state maching config value for 33 MHz CPU


	ENDIF	; already included...