diff --git a/ports/FILES b/ports/FILES index c7fb417..a6e21c9 100644 --- a/ports/FILES +++ b/ports/FILES @@ -14,6 +14,9 @@ unix/ - Architectural files for testing on unix-like systems v2pro/ - Architectural files for the Xilinx Virtex-II PRO device with embedded PowerPC 405 Processor. Supports lwIP Raw API only. (requires V2PDK - http://www.xilinx.com/ise/vii_pro/kit.htm) + +coldfire/ - Architectural files for Motorola Coldfire 5272 CPU running + under Nucleus OS. Supports DMA and ISRs in ethernet driver. Each subdirectory (may) also include: diff --git a/ports/coldfire/README b/ports/coldfire/README new file mode 100644 index 0000000..04ab9d9 --- /dev/null +++ b/ports/coldfire/README @@ -0,0 +1,231 @@ +### README --- c:/cygwin/home/dhaas/work/cfimage/lwip/arch/coldfire/ + +## +## Author: dhaas@alum.rpi.edu + +These files are a port of lwip to coldfire (specifically the MCF5272 with +on-board FEC) under the Nucleus OS. Nucleus is pretty generic so it should be +fairly easy to port this to any other embedded OS. Nucleus memory managment +is not used. It is assumed you have a working malloc (which at least +long-word aligns memory). + +The compiler used was Diab 4.3b. You will almost certainly need to change +cc.h for your compiler. + +IMPORTANT NOTE: If you use the fec driver for a different processor which has +a data cache you will need to make sure the buffer descriptors and memory +used for pbufs are not in a cachable area. Otherwise the fec driver is +guarrenteed to malfunction. The 5272 which this was written for does not +support data cache so it did not matter and malloc was used. + + +I have not released a proj directory, since my system is probably very +different than anyone trying to use this code. However my lwipopts file might +look a little different, and I reproduce that here: + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +#define NO_SYS 0 +/*#define LWIP_EVENT_API 0*/ + +/* ---------- Memory options ---------- */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +#define MEM_ALIGNMENT 4 + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#define MEM_SIZE 65000 + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#define MEMP_NUM_PBUF 16 +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#define MEMP_NUM_UDP_PCB 4 +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#define MEMP_NUM_TCP_PCB 5 +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#define MEMP_NUM_TCP_PCB_LISTEN 8 +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#define MEMP_NUM_TCP_SEG 16 + +/* The following four are used only with the sequential API and can be + set to 0 if the application only will use the raw API. */ +/* MEMP_NUM_NETBUF: the number of struct netbufs. */ +#define MEMP_NUM_NETBUF 6 +/* MEMP_NUM_NETCONN: the number of struct netconns. */ +#define MEMP_NUM_NETCONN 10 +/* MEMP_NUM_APIMSG: the number of struct api_msg, used for + communication between the TCP/IP stack and the sequential + programs. */ +#define MEMP_NUM_API_MSG 16 +/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used + for sequential API communication and incoming packets. Used in + src/api/tcpip.c. */ +#define MEMP_NUM_TCPIP_MSG 16 +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#define MEMP_NUM_SYS_TIMEOUT 3 + +/* These two control is reclaimer functions should be compiled + in. Should always be turned on (1). */ +#define MEM_RECLAIM 1 +#define MEMP_RECLAIM 1 + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ +#define PBUF_POOL_SIZE 128 + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +#define PBUF_POOL_BUFSIZE 1024 + +/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a + link level header. */ +#define PBUF_LINK_HLEN 16 + +/* SYS_ISR_PROT: Define this macro if pbuf functions are called from + an ISR and you need extra (and faster) critical region protection. */ +#define SYS_ISR_PROT 1 + +/* ---------- TCP options ---------- */ +#define LWIP_TCP 1 +#define TCP_TTL 255 + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#define TCP_QUEUE_OOSEQ 1 + +/* TCP Maximum segment size. */ +#define TCP_MSS 128 + +/* TCP sender buffer space (bytes). */ +#define TCP_SND_BUF 256 + +/* TCP sender buffer space (pbufs). This must be at least = 2 * + TCP_SND_BUF/TCP_MSS for things to work. */ +#define TCP_SND_QUEUELEN 4 * TCP_SND_BUF/TCP_MSS + +/* TCP receive window. */ +#define TCP_WND 1024 + +/* Maximum number of retransmissions of data segments. */ +#define TCP_MAXRTX 12 + +/* Maximum number of retransmissions of SYN segments. */ +#define TCP_SYNMAXRTX 4 + +/* TCP writable space (bytes). This must be less than or equal + to TCP_SND_BUF. It is the amount of space which must be + available in the tcp snd_buf for select to return writable */ +#define TCP_SNDLOWAT TCP_SND_BUF/2 + +/* ---------- ARP options ---------- */ +#define ARP_TABLE_SIZE 10 +#define ARP_QUEUEING 1 +/** + * - If enabled, cache entries are generated for every kind of ARP traffic or + * broadcast IP traffic. This enhances behaviour for sending to a dynamic set + * of hosts, for example if acting as a gateway. + * - If disabled, cache entries are generated only for IP destination addresses + * in use by lwIP or applications. This enhances performance if sending to a small, + * reasonably static number of hosts. Typically for embedded devices. + */ +#define ETHARP_ALWAYS_INSERT 0 + +/* ---------- IP options ---------- */ +/* Define IP_FORWARD to 1 if you wish to have the ability to forward + IP packets across network interfaces. If you are going to run lwIP + on a device with only one network interface, define this to 0. */ +#define IP_FORWARD 0 + +/* If defined to 1, IP options are allowed (but not parsed). If + defined to 0, all packets with IP options are dropped. */ +#define IP_OPTIONS 1 + +/* IP reassembly and segmentation.These are orthogonal even + * if they both deal with IP fragments */ +#define IP_REASSEMBLY 1 +#define IP_FRAG 1 + +/* ---------- ICMP options ---------- */ +#define ICMP_TTL 255 + + +/* ---------- DHCP options ---------- */ +/* Define LWIP_DHCP to 1 if you want DHCP configuration of + interfaces. DHCP is not implemented in lwIP 0.5.1, however, so + turning this on does currently not work. */ +#define LWIP_DHCP 0 + +/* 1 if you want to do an ARP check on the offered address + (recommended). */ +#define DHCP_DOES_ARP_CHECK 1 + +/* ---------- UDP options ---------- */ +#define LWIP_UDP 1 +#define UDP_TTL 255 + + +/* ---------- Statistics options ---------- */ +#define STATS + +#ifdef STATS +#define LINK_STATS +#define IP_STATS +#define ICMP_STATS +#define UDP_STATS +#define TCP_STATS +#define MEM_STATS +#define MEMP_STATS +#define PBUF_STATS +#define SYS_STATS +#endif /* STATS */ + + +#define LWIP_COMPAT_SOCKETS +#endif /* __LWIPOPTS_H__ */ + + + + + + + diff --git a/ports/coldfire/include/arch/cc.h b/ports/coldfire/include/arch/cc.h new file mode 100644 index 0000000..682844b --- /dev/null +++ b/ports/coldfire/include/arch/cc.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2001-2003, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: cc.h,v 1.1 2003/01/18 18:47:22 jani Exp $ + */ +#ifndef __CC_H__ +#define __CC_H__ + +#include + +// typedef unsigned char u8_t; +// typedef signed char s8_t; +// typedef unsigned short u16_t; +// typedef signed short s16_t; +// typedef unsigned long u32_t; +// typedef signed long s32_t; + +typedef u32_t mem_ptr_t; + +#define PACK_STRUCT_BEGIN #pragma pack(1,1,0) +#define PACK_STRUCT_STRUCT +#define ALIGN_STRUCT_8_BEGIN #pragma pack(1,8,0) +#define ALIGN_STRUCT_END #pragma pack() +#define PACK_STRUCT_END #pragma pack() +#define PACK_STRUCT_FIELD(x) x + + +#define _SYS_TYPES_FD_SET +#define NBBY 8 /* number of bits in a byte */ + +#ifndef FD_SETSIZE +#define FD_SETSIZE 64 +#endif /* FD_SETSIZE */ + +typedef long fd_mask; +#define NFDBITS (sizeof (fd_mask) * NBBY) /* bits per mask */ +#ifndef howmany +#define howmany(x,y) (((x)+((y)-1))/(y)) +#endif /* howmany */ + +typedef struct _types_fd_set { + fd_mask fds_bits[howmany(FD_SETSIZE, NFDBITS)]; +} _types_fd_set; + +#define fd_set _types_fd_set + +#define FD_SET(n, p) ((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS))) +#define FD_CLR(n, p) ((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS))) +#define FD_ISSET(n, p) ((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS))) +#define FD_ZERO(p) do { \ + size_t __i; \ + char *__tmp = (char *)p; \ + for (__i = 0; __i < sizeof (*(p)); ++__i) \ + *__tmp++ = 0; \ +} while (0) + +#endif /* __CC_H__ */ diff --git a/ports/coldfire/include/arch/cpu.h b/ports/coldfire/include/arch/cpu.h new file mode 100644 index 0000000..c2c6788 --- /dev/null +++ b/ports/coldfire/include/arch/cpu.h @@ -0,0 +1,43 @@ +/* @(#)cpu.h + * Copyright (c) 2001-2003, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: David Haas + * + */ + +#ifndef _CPU_H +#define _CPU_H 1 + +#define BYTE_ORDER BIG_ENDIAN +#define IMM_ADDRESS (0x10000000) +#define FEC_LEVEL 4 + +#endif /* _CPU_H */ + diff --git a/ports/coldfire/include/arch/errno.h b/ports/coldfire/include/arch/errno.h new file mode 100644 index 0000000..edd7883 --- /dev/null +++ b/ports/coldfire/include/arch/errno.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: David Haas + * + * $Id: + */ +#ifndef __ERRNO_H__ +#define __ERRNO_H__ + +/* This can be used to test whether errno is implemented */ +#define ERRNO + +#define errno (*sys_arch_errno()) + + +/* Error numbers */ +#define EBADF 9 /* Bad file number */ +#define EINVAL 22 /* Invalid argument */ +#define ENOBUFS 105 /* No buffer space available */ +#define EWOULDBLOCK 40 /* We would have blocked if this was'nt non-blocking i/o */ +#endif diff --git a/ports/coldfire/include/arch/lib.h b/ports/coldfire/include/arch/lib.h new file mode 100644 index 0000000..b2c9cea --- /dev/null +++ b/ports/coldfire/include/arch/lib.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2001-2003, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: lib.h,v 1.1 2003/01/18 18:47:22 jani Exp $ + */ +#ifndef __LIB_H__ +#define __LIB_H__ + +#include + +#endif /* __LIB_H__ */ diff --git a/ports/coldfire/include/arch/mcf5272.h b/ports/coldfire/include/arch/mcf5272.h new file mode 100644 index 0000000..70427ed --- /dev/null +++ b/ports/coldfire/include/arch/mcf5272.h @@ -0,0 +1,2005 @@ +/* + * Copyright (c) 2001-2003, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * + * Notes: This file provided by Motorola as part of their example code. + */ + +#ifndef _CPU_MCF5272_H +#define _CPU_MCF5272_H + +/***********************************************************************/ +/* + * Misc. Defines + */ + +#ifdef FALSE +#undef FALSE +#endif +#define FALSE (0) + +#ifdef TRUE +#undef TRUE +#endif +#define TRUE (1) + +#ifdef NULL +#undef NULL +#endif +#define NULL (0) + +/***********************************************************************/ +/* + * The basic data types + */ + +typedef volatile unsigned char vuint8; /* 8 bits */ +typedef volatile unsigned short int vuint16; /* 16 bits */ +typedef volatile unsigned long int vuint32; /* 32 bits */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +/***********************************************************************/ +/* + * Common M68K & ColdFire definitions + */ + +#define ADDRESS uint32 +#define INSTRUCTION uint16 +#define ILLEGAL 0x4AFC +#define CPU_WORD_SIZE 16 + +/***********************************************************************/ + +/* + * Routines and macros for accessing Input/Output devices + */ + +#define cpu_iord_8(ADDR) *((volatile uint8 *)(ADDR)) +#define cpu_iord_16(ADDR) *((volatile uint16 *)(ADDR)) +#define cpu_iord_32(ADDR) *((volatile uint32 *)(ADDR)) + +#define cpu_iowr_8(ADDR,DATA) *((volatile uint8 *)(ADDR)) = (DATA) +#define cpu_iowr_16(ADDR,DATA) *((volatile uint16 *)(ADDR)) = (DATA) +#define cpu_iowr_32(ADDR,DATA) *((volatile uint32 *)(ADDR)) = (DATA) + +/***********************************************************************/ + +#define MCF5200_SR_T (0x8000) +#define MCF5200_SR_S (0x2000) +#define MCF5200_SR_M (0x1000) +#define MCF5200_SR_IPL (0x0700) +#define MCF5200_SR_IPL_0 (0x0000) +#define MCF5200_SR_IPL_1 (0x0100) +#define MCF5200_SR_IPL_2 (0x0200) +#define MCF5200_SR_IPL_3 (0x0300) +#define MCF5200_SR_IPL_4 (0x0400) +#define MCF5200_SR_IPL_5 (0x0500) +#define MCF5200_SR_IPL_6 (0x0600) +#define MCF5200_SR_IPL_7 (0x0700) +#define MCF5200_SR_X (0x0010) +#define MCF5200_SR_N (0x0008) +#define MCF5200_SR_Z (0x0004) +#define MCF5200_SR_V (0x0002) +#define MCF5200_SR_C (0x0001) + +/***********************************************************************/ + +/* + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + */ + +#define MCF5200_RD_SF_FORMAT(PTR) \ + ((*((uint16 *)(PTR)) >> 12) & 0x00FF) + +#define MCF5200_RD_SF_VECTOR(PTR) \ + ((*((uint16 *)(PTR)) >> 2) & 0x00FF) + +#define MCF5200_RD_SF_FS(PTR) \ + ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) + +#define MCF5200_SF_SR(PTR) *((uint16 *)(PTR)+1) +#define MCF5200_SF_PC(PTR) *((uint32 *)(PTR)+1) + +#if 0 +typedef struct +{ + uint16 SR; + uint16 FS_FMT_VECTOR_FS; + uint32 PC; +} MCF5200_STACK_FRAME; +#endif + + +/********************************************************************** +* +* Macro for computing address of on-chip peripheral registers +* +***********************************************************************/ + +#define Mcf5272_addr(IMMP,OFFSET) ((void *)&((uint8 *)IMMP)[OFFSET]) + +/* Macro that returns a pointer to the Internal Memory Map */ +#define mcf5272_get_immp() ((MCF5272_IMM *)(IMM_ADDRESS)) + +/********************************************************************** +* +* Macros for accessing the on-chip I/O resources +* +***********************************************************************/ + +#define Mcf5272_iord(IMMP,OFFSET,SIZE) \ + *(volatile uint ## SIZE *)(Mcf5272_addr(IMMP,OFFSET)) + +#define Mcf5272_iowr(IMMP,OFFSET,SIZE,DATA) \ + *(volatile uint ## SIZE *)(Mcf5272_addr(IMMP,OFFSET)) = (DATA) + +/********************************************************************** +* +* CPU Space Registers +* +***********************************************************************/ + +/* Bit level definitions and macros */ +#define MCF5272_CACR_CENB (0x80000000) +#define MCF5272_CACR_CFRZ (0x08000000) +#define MCF5272_CACR_CINV (0x01000000) +#define MCF5272_CACR_CMOD (0x00000200) +#define MCF5272_CACR_CWRP (0x00000020) +#define MCF5272_CACR_CLNF_00 (0x00000000) +#define MCF5272_CACR_CLNF_01 (0x00000001) +#define MCF5272_CACR_CLNF_10 (0x00000002) + +#define MCF5272_ACR_BASE(a) ((a)&0xFF000000) +#define MCF5272_ACR_MASK(a) (((a)&0xFF000000) >> 8) +#define MCF5272_ACR_EN (0x00008000) +#define MCF5272_ACR_S_USER (0x00000000) +#define MCF5272_ACR_S_SUPER (0x00002000) +#define MCF5272_ACR_S_IGNORE (0x00006000) +#define MCF5272_ACR_ENIB (0x00000080) +#define MCF5272_ACR_CM (0x00000040) +#define MCF5272_ACR_WP (0x00000004) + +#define MCF5272_SRAMBAR_BASE(a) ((a)&0xFFFFF000) +#define MCF5272_SRAMBAR_WP (0x00000100) +#define MCF5272_SRAMBAR_CI (0x00000020) +#define MCF5272_SRAMBAR_SC (0x00000010) +#define MCF5272_SRAMBAR_SD (0x00000008) +#define MCF5272_SRAMBAR_UC (0x00000004) +#define MCF5272_SRAMBAR_UD (0x00000002) +#define MCF5272_SRAMBAR_V (0x00000001) + +#define MCF5272_ROMBAR_BASE(a) ((a)&0xFFFFF000) +#define MCF5272_ROMBAR_WP (0x00000100) +#define MCF5272_ROMBAR_CI (0x00000080) +#define MCF5272_ROMBAR_SC (0x00000040) +#define MCF5272_ROMBAR_SD (0x00000020) +#define MCF5272_ROMBAR_UC (0x00000004) +#define MCF5272_ROMBAR_UD (0x00000002) +#define MCF5272_ROMBAR_V (0x00000001) + +#define MCF5272_MBAR_BASE(a) ((a)&0xFFFFFC00) +#define MCF5272_MBAR_SC (0x00000010) +#define MCF5272_MBAR_SD (0x00000008) +#define MCF5272_MBAR_UC (0x00000004) +#define MCF5272_MBAR_UD (0x00000002) +#define MCF5272_MBAR_V (0x00000001) + +/********************************************************************** +* +* System Configuration Registers +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_SIM_MBAR (0x0000) +#define MCF5272_SIM_SCR (0x0004) +#define MCF5272_SIM_SPR (0x0006) +#define MCF5272_SIM_PMR (0x0008) +#define MCF5272_SIM_ALPR (0x000E) +#define MCF5272_SIM_DIR (0x0010) + +/* Read access macros for general use */ +#define MCF5272_RD_SIM_MBAR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_MBAR,32) +#define MCF5272_RD_SIM_SCR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_SCR,16) +#define MCF5272_RD_SIM_SPR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_SPR,16) +#define MCF5272_RD_SIM_PMR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PMR,32) +#define MCF5272_RD_SIM_DIR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_DIR,32) + +/* Write access macros for general use */ +#define MCF5272_WR_SIM_SCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_SCR,16,DATA) +#define MCF5272_WR_SIM_SPR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_SPR,16,DATA) +#define MCF5272_WR_SIM_PMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_PMR,32,DATA) +#define MCF5272_WR_SIM_ALPR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_ALPR,16,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_SIM_SCR_HRST 0x1000 +#define MCF5272_SIM_SCR_DRAMRST 0x3000 +#define MCF5272_SIM_SCR_SWTR 0x2000 +#define MCF5272_SIM_SCR_AR 0x0080 +#define MCF5272_SIM_SCR_SOFT_RES 0x0040 +#define MCF5272_SIM_SCR_HWWD_128 0x0000 +#define MCF5272_SIM_SCR_HWWD_256 0x0001 +#define MCF5272_SIM_SCR_HWWD_512 0x0002 +#define MCF5272_SIM_SCR_HWWD_1024 0x0003 +#define MCF5272_SIM_SCR_HWWD_2048 0x0004 +#define MCF5272_SIM_SCR_HWWD_4096 0x0005 +#define MCF5272_SIM_SCR_HWWD_8192 0x0006 +#define MCF5272_SIM_SCR_HWWD_16384 0x0007 + +#define MCF5272_SIM_SPR_ADC 0x8000 +#define MCF5272_SIM_SPR_ADCEN 0x0080 +#define MCF5272_SIM_SPR_WPV 0x4000 +#define MCF5272_SIM_SPR_WPVEN 0x0040 +#define MCF5272_SIM_SPR_SMV 0x2000 +#define MCF5272_SIM_SPR_SMVEN 0x0020 +#define MCF5272_SIM_SPR_SBE 0x1000 +#define MCF5272_SIM_SPR_SBEEN 0x0010 +#define MCF5272_SIM_SPR_HWT 0x0800 +#define MCF5272_SIM_SPR_HWTEN 0x0008 +#define MCF5272_SIM_SPR_RPV 0x0400 +#define MCF5272_SIM_SPR_RPVEN 0x0004 +#define MCF5272_SIM_SPR_EXT 0x0200 +#define MCF5272_SIM_SPR_EXTEN 0x0002 +#define MCF5272_SIM_SPR_SUV 0x0100 +#define MCF5272_SIM_SPR_SUVEN 0x0001 + +#define MCF5272_SIM_PMR_BDMPDN 0x80000000 +#define MCF5272_SIM_PMR_ENETPDN 0x04000000 +#define MCF5272_SIM_PMR_PLIPPDN 0x02000000 +#define MCF5272_SIM_PMR_DRAMPDN 0x01000000 +#define MCF5272_SIM_PMR_DMAPDN 0x00800000 +#define MCF5272_SIM_PMR_PWMPDN 0x00400000 +#define MCF5272_SIM_PMR_QSPIPDN 0x00200000 +#define MCF5272_SIM_PMR_TIMERPDN 0x00100000 +#define MCF5272_SIM_PMR_GPIOPDN 0x00080000 +#define MCF5272_SIM_PMR_USBPDN 0x00040000 +#define MCF5272_SIM_PMR_UART1PDN 0x00020000 +#define MCF5272_SIM_PMR_UART0PDN 0x00010000 +#define MCF5272_SIM_PMR_USBWK 0x00000400 +#define MCF5272_SIM_PMR_UART1WK 0x00000200 +#define MCF5272_SIM_PMR_UART0WK 0x00000100 +#define MCF5272_SIM_PMR_MOS 0x00000020 +#define MCF5272_SIM_PMR_SLPEN 0x00000010 + +/********************************************************************** +* +* Interrupt Controller Registers +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_SIM_ICR1 (0x0020) +#define MCF5272_SIM_ICR2 (0x0024) +#define MCF5272_SIM_ICR3 (0x0028) +#define MCF5272_SIM_ICR4 (0x002C) +#define MCF5272_SIM_ISR (0x0030) +#define MCF5272_SIM_PITR (0x0034) +#define MCF5272_SIM_PIWR (0x0038) +#define MCF5272_SIM_PIVR (0x003F) + +/* Read access macros for general use */ +#define MCF5272_RD_SIM_ICR1(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR1,32) +#define MCF5272_RD_SIM_ICR2(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR2,32) +#define MCF5272_RD_SIM_ICR3(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR3,32) +#define MCF5272_RD_SIM_ICR4(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ICR4,32) +#define MCF5272_RD_SIM_ISR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_ISR,32) +#define MCF5272_RD_SIM_PITR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PITR,32) +#define MCF5272_RD_SIM_PIWR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PIWR,32) +#define MCF5272_RD_SIM_PIVR(IMMP) Mcf5272_iord(IMMP,MCF5272_SIM_PIVR,8) + +/* Write access macros for general use */ +#define MCF5272_WR_SIM_ICR1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_ICR1,32,DATA) +#define MCF5272_WR_SIM_ICR2(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_ICR2,32,DATA) +#define MCF5272_WR_SIM_ICR3(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_ICR3,32,DATA) +#define MCF5272_WR_SIM_ICR4(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_ICR4,32,DATA) +#define MCF5272_WR_SIM_PITR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_PITR,32,DATA) +#define MCF5272_WR_SIM_PIWR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_PIWR,32,DATA) +#define MCF5272_WR_SIM_PIVR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SIM_PIVR,8,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_SIM_ICR_INT1_IL(a) ( 0x80000000 | (((a)&0x07)<<28) ) +#define MCF5272_SIM_ICR_INT2_IL(a) ( 0x08000000 | (((a)&0x07)<<24) ) +#define MCF5272_SIM_ICR_INT3_IL(a) ( 0x00800000 | (((a)&0x07)<<20) ) +#define MCF5272_SIM_ICR_INT4_IL(a) ( 0x00080000 | (((a)&0x07)<<16) ) +#define MCF5272_SIM_ICR_TMR0_IL(a) ( 0x00008000 | (((a)&0x07)<<12) ) +#define MCF5272_SIM_ICR_TMR1_IL(a) ( 0x00000800 | (((a)&0x07)<<8) ) +#define MCF5272_SIM_ICR_TMR2_IL(a) ( 0x00000080 | (((a)&0x07)<<4) ) +#define MCF5272_SIM_ICR_TMR3_IL(a) ( 0x00000008 | ((a)&0x07) ) +#define MCF5272_SIM_ICR_TMR_IL(a,x) ( (0x8 | ((a)&0x07)) << ((3-x)*4)) + +#define MCF5272_SIM_ICR_UART0_IL(a) ( 0x80000000 | (((a)&0x07)<<28) ) +#define MCF5272_SIM_ICR_UART1_IL(a) ( 0x08000000 | (((a)&0x07)<<24) ) +#define MCF5272_SIM_ICR_PLIP_IL(a) ( 0x00800000 | (((a)&0x07)<<20) ) +#define MCF5272_SIM_ICR_PLIA_IL(a) ( 0x00080000 | (((a)&0x07)<<16) ) +#define MCF5272_SIM_ICR_USB0_IL(a) ( 0x00008000 | (((a)&0x07)<<12) ) +#define MCF5272_SIM_ICR_USB1_IL(a) ( 0x00000800 | (((a)&0x07)<<8) ) +#define MCF5272_SIM_ICR_USB2_IL(a) ( 0x00000800 | (((a)&0x07)<<4) ) +#define MCF5272_SIM_ICR_USB3_IL(a) ( 0x00000800 | ((a)&0x07) ) + +#define MCF5272_SIM_ICR_USB4_IL(a) ( 0x80000000 | (((a)&0x07)<<28) ) +#define MCF5272_SIM_ICR_USB5_IL(a) ( 0x08000000 | (((a)&0x07)<<24) ) +#define MCF5272_SIM_ICR_USB6_IL(a) ( 0x00800000 | (((a)&0x07)<<20) ) +#define MCF5272_SIM_ICR_USB7_IL(a) ( 0x00080000 | (((a)&0x07)<<16) ) +#define MCF5272_SIM_ICR_DMA_IL(a) ( 0x00008000 | (((a)&0x07)<<12) ) +#define MCF5272_SIM_ICR_ERX_IL(a) ( 0x00000800 | (((a)&0x07)<<8) ) +#define MCF5272_SIM_ICR_ETX_IL(a) ( 0x00000080 | (((a)&0x07)<<4) ) +#define MCF5272_SIM_ICR_ENTC_IL(a) ( 0x00000008 | ((a)&0x07) ) + +#define MCF5272_SIM_ICR_QSPI_IL(a) ( 0x80000000 | (((a)&0x07)<<28) ) +#define MCF5272_SIM_ICR_INT5_IL(a) ( 0x08000000 | (((a)&0x07)<<24) ) +#define MCF5272_SIM_ICR_INT6_IL(a) ( 0x00800000 | (((a)&0x07)<<20) ) +#define MCF5272_SIM_ICR_SWTO_IL(a) ( 0x00080000 | (((a)&0x07)<<16) ) + +#define MCF5272_SIM_PITR_POS_EDGE (0xF0000060) +#define MCF5272_SIM_PITR_NEG_EDGE (0x00000000) + +#define MCF5272_SIM_PIWR_INT1 (0x80000000) +#define MCF5272_SIM_PIWR_INT2 (0x40000000) +#define MCF5272_SIM_PIWR_INT3 (0x20000000) +#define MCF5272_SIM_PIWR_INT4 (0x10000000) +#define MCF5272_SIM_PIWR_TMR0 (0x08000000) +#define MCF5272_SIM_PIWR_TMR1 (0x04000000) +#define MCF5272_SIM_PIWR_TMR2 (0x02000000) +#define MCF5272_SIM_PIWR_TMR3 (0x01000000) +#define MCF5272_SIM_PIWR_UART0 (0x00800000) +#define MCF5272_SIM_PIWR_UART1 (0x00400000) +#define MCF5272_SIM_PIWR_PLIP (0x00200000) +#define MCF5272_SIM_PIWR_PLIA (0x00100000) +#define MCF5272_SIM_PIWR_USB_0 (0x00080000) +#define MCF5272_SIM_PIWR_USB_1 (0x00040000) +#define MCF5272_SIM_PIWR_USB_2 (0x00020000) +#define MCF5272_SIM_PIWR_USB_3 (0x00010000) +#define MCF5272_SIM_PIWR_USB_4 (0x00008000) +#define MCF5272_SIM_PIWR_USB_5 (0x00004000) +#define MCF5272_SIM_PIWR_USB_6 (0x00002000) +#define MCF5272_SIM_PIWR_USB_7 (0x00001000) +#define MCF5272_SIM_PIWR_DMA (0x00000800) +#define MCF5272_SIM_PIWR_ERx (0x00000400) +#define MCF5272_SIM_PIWR_ETx (0x00000200) +#define MCF5272_SIM_PIWR_ENTC (0x00000100) +#define MCF5272_SIM_PIWR_QSPI (0x00000080) +#define MCF5272_SIM_PIWR_INT5 (0x00000040) +#define MCF5272_SIM_PIWR_INT6 (0x00000020) +#define MCF5272_SIM_PIWR_SWTO (0x00000010) + +#define MCF5272_SIM_PIVR_IL(a) (((a)&0x07)<<5) +#define MCF5272_SIM_PIVR_NORMAL (0x40) + +/********************************************************************** + * + * Interrupt Vectors + * + **********************************************************************/ +#define MCF5272_VECTOR_INT1 65 +#define MCF5272_VECTOR_INT2 66 +#define MCF5272_VECTOR_INT3 67 +#define MCF5272_VECTOR_INT4 68 +#define MCF5272_VECTOR_TMR1 69 +#define MCF5272_VECTOR_TMR2 70 +#define MCF5272_VECTOR_TMR3 71 +#define MCF5272_VECTOR_TMR4 72 +#define MCF5272_VECTOR_UART1 73 +#define MCF5272_VECTOR_UART2 74 +#define MCF5272_VECTOR_PLIP 75 +#define MCF5272_VECTOR_PLIA 76 +#define MCF5272_VECTOR_USB0 77 +#define MCF5272_VECTOR_USB1 78 +#define MCF5272_VECTOR_USB2 79 +#define MCF5272_VECTOR_USB3 80 +#define MCF5272_VECTOR_USB4 81 +#define MCF5272_VECTOR_USB5 82 +#define MCF5272_VECTOR_USB6 83 +#define MCF5272_VECTOR_USB7 84 +#define MCF5272_VECTOR_DMA 85 +#define MCF5272_VECTOR_ERx 86 +#define MCF5272_VECTOR_ETx 87 +#define MCF5272_VECTOR_ENTC 88 +#define MCF5272_VECTOR_QSPI 89 +#define MCF5272_VECTOR_INT5 90 +#define MCF5272_VECTOR_INT6 91 +#define MCF5272_VECTOR_SWTO 92 + +/********************************************************************** +* +* Chip Select Registers +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_CS_CSBR0 (0x0040) +#define MCF5272_CS_CSOR0 (0x0044) +#define MCF5272_CS_CSBR1 (0x0048) +#define MCF5272_CS_CSOR1 (0x004C) +#define MCF5272_CS_CSBR2 (0x0050) +#define MCF5272_CS_CSOR2 (0x0054) +#define MCF5272_CS_CSBR3 (0x0058) +#define MCF5272_CS_CSOR3 (0x005C) +#define MCF5272_CS_CSBR4 (0x0060) +#define MCF5272_CS_CSOR4 (0x0064) +#define MCF5272_CS_CSBR5 (0x0068) +#define MCF5272_CS_CSOR5 (0x006C) +#define MCF5272_CS_CSBR6 (0x0070) +#define MCF5272_CS_CSOR6 (0x0074) +#define MCF5272_CS_CSBR7 (0x0078) +#define MCF5272_CS_CSOR7 (0x007C) + +/* Read access macros for general use */ +#define MCF5272_RD_CS_CSBR0(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR0,32) +#define MCF5272_RD_CS_CSOR0(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR0,32) +#define MCF5272_RD_CS_CSBR1(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR1,32) +#define MCF5272_RD_CS_CSOR1(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR1,32) +#define MCF5272_RD_CS_CSBR2(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR2,32) +#define MCF5272_RD_CS_CSOR2(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR2,32) +#define MCF5272_RD_CS_CSBR3(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR3,32) +#define MCF5272_RD_CS_CSOR3(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR3,32) +#define MCF5272_RD_CS_CSBR4(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR4,32) +#define MCF5272_RD_CS_CSOR4(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR4,32) +#define MCF5272_RD_CS_CSBR5(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR5,32) +#define MCF5272_RD_CS_CSOR5(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR5,32) +#define MCF5272_RD_CS_CSBR6(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR6,32) +#define MCF5272_RD_CS_CSOR6(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR6,32) +#define MCF5272_RD_CS_CSBR7(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSBR7,32) +#define MCF5272_RD_CS_CSOR7(IMMP) Mcf5272_iord(IMMP,MCF5272_CS_CSOR7,32) + +/* Write access macros for general use */ +#define MCF5272_WR_CS_CSBR0(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR0,32,DATA) +#define MCF5272_WR_CS_CSOR0(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR0,32,DATA) +#define MCF5272_WR_CS_CSBR1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR1,32,DATA) +#define MCF5272_WR_CS_CSOR1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR1,32,DATA) +#define MCF5272_WR_CS_CSBR2(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR2,32,DATA) +#define MCF5272_WR_CS_CSOR2(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR2,32,DATA) +#define MCF5272_WR_CS_CSBR3(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR3,32,DATA) +#define MCF5272_WR_CS_CSOR3(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR3,32,DATA) +#define MCF5272_WR_CS_CSBR4(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR4,32,DATA) +#define MCF5272_WR_CS_CSOR4(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR4,32,DATA) +#define MCF5272_WR_CS_CSBR5(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR5,32,DATA) +#define MCF5272_WR_CS_CSOR5(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR5,32,DATA) +#define MCF5272_WR_CS_CSBR6(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR6,32,DATA) +#define MCF5272_WR_CS_CSOR6(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR6,32,DATA) +#define MCF5272_WR_CS_CSBR7(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSBR7,32,DATA) +#define MCF5272_WR_CS_CSOR7(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_CS_CSOR7,32,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_CS_BR_BASE(a) ((a)&0xFFFFF000) + +#define MCF5272_CS_OR_MASK_32M (0xFE000000) +#define MCF5272_CS_OR_MASK_16M (0xFF000000) +#define MCF5272_CS_OR_MASK_8M (0xFF800000) +#define MCF5272_CS_OR_MASK_4M (0xFFC00000) +#define MCF5272_CS_OR_MASK_2M (0xFFE00000) +#define MCF5272_CS_OR_MASK_1M (0xFFF00000) +#define MCF5272_CS_OR_MASK_512K (0xFFF80000) +#define MCF5272_CS_OR_MASK_256K (0xFFFC0000) +#define MCF5272_CS_OR_MASK_128K (0xFFFE0000) +#define MCF5272_CS_OR_MASK_64K (0xFFFF0000) +#define MCF5272_CS_OR_MASK_32K (0xFFFF8000) +#define MCF5272_CS_OR_MASK_16K (0xFFFFC000) +#define MCF5272_CS_OR_MASK_8K (0xFFFFE000) +#define MCF5272_CS_OR_MASK_4K (0xFFFFF000) +#define MCF5272_CS_OR_WS_MASK (0x007C) +#define MCF5272_CS_OR_WS(a) (((a)&0x1F)<<2) +#define MCF5272_CS_OR_BRST (0x0100) +#define MCF5272_CS_OR_RD (0x0003) +#define MCF5272_CS_OR_WR (0x0001) + +#define MCF5272_CS_BR_PS_8 (0x0100) +#define MCF5272_CS_BR_PS_16 (0x0200) +#define MCF5272_CS_BR_PS_32 (0x0000) +#define MCF5272_CS_BR_PS_LINE (0x0300) +#define MCF5272_CS_BR_ROM (0x0000) +#define MCF5272_CS_BR_SRAM (0x0000) +#define MCF5272_CS_BR_SRAM_8 (0x0C00) +#define MCF5272_CS_BR_SDRAM (0x0400) +#define MCF5272_CS_BR_ISA (0x0800) +#define MCF5272_CS_BR_SV (0x0080) +#define MCF5272_CS_BR_EN (0x0001) + +/********************************************************************** +* +* Ports Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_GPIO_PACNT (0x0080) +#define MCF5272_GPIO_PADDR (0x0084) +#define MCF5272_GPIO_PADAT (0x0086) +#define MCF5272_GPIO_PBCNT (0x0088) +#define MCF5272_GPIO_PBDDR (0x008C) +#define MCF5272_GPIO_PBDAT (0x008E) +#define MCF5272_GPIO_PCDDR (0x0094) +#define MCF5272_GPIO_PCDAT (0x0096) +#define MCF5272_GPIO_PDCNT (0x0098) + +/* Read access macros for general use */ +#define MCF5272_RD_GPIO_PACNT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PACNT,32) +#define MCF5272_RD_GPIO_PADDR(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PADDR,16) +#define MCF5272_RD_GPIO_PADAT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PADAT,16) +#define MCF5272_RD_GPIO_PBCNT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PBCNT,32) +#define MCF5272_RD_GPIO_PBDDR(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PBDDR,16) +#define MCF5272_RD_GPIO_PBDAT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PBDAT,16) +#define MCF5272_RD_GPIO_PCDDR(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PCDDR,16) +#define MCF5272_RD_GPIO_PCDAT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PCDAT,16) +#define MCF5272_RD_GPIO_PDCNT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PDCNT,32) + +/* Write access macros for general use */ +#define MCF5272_WR_GPIO_PACNT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PACNT,32,DATA) +#define MCF5272_WR_GPIO_PADDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PADDR,16,DATA) +#define MCF5272_WR_GPIO_PADAT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PADAT,16,DATA) +#define MCF5272_WR_GPIO_PBCNT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PBCNT,32,DATA) +#define MCF5272_WR_GPIO_PBDDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PBDDR,16,DATA) +#define MCF5272_WR_GPIO_PBDAT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PBDAT,16,DATA) +#define MCF5272_WR_GPIO_PCDDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PCDDR,16,DATA) +#define MCF5272_WR_GPIO_PCDAT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PCDAT,16,DATA) +#define MCF5272_WR_GPIO_PDCNT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_GPIO_PDCNT,32,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_GPIO_DDR15_INPUT (~0x80) +#define MCF5272_GPIO_DDR15_OUTPUT ( 0x80) +#define MCF5272_GPIO_DDR14_INPUT (~0x40) +#define MCF5272_GPIO_DDR14_OUTPUT ( 0x40) +#define MCF5272_GPIO_DDR13_INPUT (~0x20) +#define MCF5272_GPIO_DDR13_OUTPUT ( 0x20) +#define MCF5272_GPIO_DDR12_INPUT (~0x10) +#define MCF5272_GPIO_DDR12_OUTPUT ( 0x10) +#define MCF5272_GPIO_DDR11_INPUT (~0x08) +#define MCF5272_GPIO_DDR11_OUTPUT ( 0x08) +#define MCF5272_GPIO_DDR10_INPUT (~0x04) +#define MCF5272_GPIO_DDR10_OUTPUT ( 0x04) +#define MCF5272_GPIO_DDR9_INPUT (~0x02) +#define MCF5272_GPIO_DDR9_OUTPUT ( 0x02) +#define MCF5272_GPIO_DDR8_INPUT (~0x01) +#define MCF5272_GPIO_DDR8_OUTPUT ( 0x01) +#define MCF5272_GPIO_DDR7_INPUT (~0x80) +#define MCF5272_GPIO_DDR7_OUTPUT ( 0x80) +#define MCF5272_GPIO_DDR6_INPUT (~0x40) +#define MCF5272_GPIO_DDR6_OUTPUT ( 0x40) +#define MCF5272_GPIO_DDR5_INPUT (~0x20) +#define MCF5272_GPIO_DDR5_OUTPUT ( 0x20) +#define MCF5272_GPIO_DDR4_INPUT (~0x10) +#define MCF5272_GPIO_DDR4_OUTPUT ( 0x10) +#define MCF5272_GPIO_DDR3_INPUT (~0x08) +#define MCF5272_GPIO_DDR3_OUTPUT ( 0x08) +#define MCF5272_GPIO_DDR2_INPUT (~0x04) +#define MCF5272_GPIO_DDR2_OUTPUT ( 0x04) +#define MCF5272_GPIO_DDR1_INPUT (~0x02) +#define MCF5272_GPIO_DDR1_OUTPUT ( 0x02) +#define MCF5272_GPIO_DDR0_INPUT (~0x01) +#define MCF5272_GPIO_DDR0_OUTPUT ( 0x01) + +#define MCF5272_GPIO_DAT15 ( 0x80) +#define MCF5272_GPIO_DAT14 ( 0x40) +#define MCF5272_GPIO_DAT13 ( 0x20) +#define MCF5272_GPIO_DAT12 ( 0x10) +#define MCF5272_GPIO_DAT11 ( 0x08) +#define MCF5272_GPIO_DAT10 ( 0x04) +#define MCF5272_GPIO_DAT9 ( 0x02) +#define MCF5272_GPIO_DAT8 ( 0x01) +#define MCF5272_GPIO_DAT7 ( 0x80) +#define MCF5272_GPIO_DAT6 ( 0x40) +#define MCF5272_GPIO_DAT5 ( 0x20) +#define MCF5272_GPIO_DAT4 ( 0x10) +#define MCF5272_GPIO_DAT3 ( 0x08) +#define MCF5272_GPIO_DAT2 ( 0x04) +#define MCF5272_GPIO_DAT1 ( 0x02) +#define MCF5272_GPIO_DAT0 ( 0x01) + + +/********************************************************************** +* +* QSPI Module Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_QSPI_QMR (0x00A0) +#define MCF5272_QSPI_QDLYR (0x00A4) +#define MCF5272_QSPI_QWR (0x00A8) +#define MCF5272_QSPI_QIR (0x00AC) +#define MCF5272_QSPI_QAR (0x00B0) +#define MCF5272_QSPI_QDR (0x00B4) + +/* Read access macros for general use */ +#define MCF5272_RD_QSPI_QMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_QSPI_QMR,16) +#define MCF5272_RD_QSPI_QDLYR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_QSPI_QDLYR,16) +#define MCF5272_RD_QSPI_QWR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_QSPI_QWR,16) +#define MCF5272_RD_QSPI_QIR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_QSPI_QIR,16) +#define MCF5272_RD_QSPI_QAR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_QSPI_QAR,16) +#define MCF5272_RD_QSPI_QDR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_QSPI_QDR,16) + +/* Write access macros for general use */ +#define MCF5272_WR_QSPI_QMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_QSPI_QMR,16,DATA) +#define MCF5272_WR_QSPI_QDLYR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_QSPI_QDLYR,16,DATA) +#define MCF5272_WR_QSPI_QWR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_QSPI_QWR,16,DATA) +#define MCF5272_WR_QSPI_QIR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_QSPI_QIR,16,DATA) +#define MCF5272_WR_QSPI_QAR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_QSPI_QAR,16,DATA) +#define MCF5272_WR_QSPI_QDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_QSPI_QDR,16,DATA) + + +/********************************************************************** +* +* PWM Module Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_PWM_PWMCR1 (0x00C0) +#define MCF5272_PWM_PWMCR2 (0x00C4) +#define MCF5272_PWM_PWMCR3 (0x00C8) +#define MCF5272_PWM_PWMWD1 (0x00D0) +#define MCF5272_PWM_PWMWD2 (0x00D4) +#define MCF5272_PWM_PWMWD3 (0x00D8) + +/* Read access macros for general use */ +#define MCF5272_RD_PWM_PWMCR1(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR1,8) +#define MCF5272_RD_PWM_PWMCR2(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR2,8) +#define MCF5272_RD_PWM_PWMCR3(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR3,8) +#define MCF5272_RD_PWM_PWMWD1(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD1,8) +#define MCF5272_RD_PWM_PWMWD2(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD2,8) +#define MCF5272_RD_PWM_PWMWD3(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD3,8) + +/* Write access macros for general use */ +#define MCF5272_WR_PWM_PWMCR1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR1,8,DATA) +#define MCF5272_WR_PWM_PWMCR2(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR2,8,DATA) +#define MCF5272_WR_PWM_PWMCR3(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR3,8,DATA) +#define MCF5272_WR_PWM_PWMWD1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD1,8,DATA) +#define MCF5272_WR_PWM_PWMWD2(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD2,8,DATA) +#define MCF5272_WR_PWM_PWMWD3(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD3,8,DATA) + +/********************************************************************** +* +* DMA Module Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_DMA_DCMR (0x00E0) +#define MCF5272_DMA_DCIR (0x00E6) +#define MCF5272_DMA_DBCR (0x00E8) +#define MCF5272_DMA_DSAR (0x00EC) +#define MCF5272_DMA_DDAR (0x00F0) + +/* Read access macros for general use */ +#define MCF5272_RD_DMA_DCMR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DCMR,32) +#define MCF5272_RD_DMA_DCIR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DCIR,16) +#define MCF5272_RD_DMA_DBCR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DBCR,32) +#define MCF5272_RD_DMA_DSAR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DSAR,32) +#define MCF5272_RD_DMA_DDAR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DDAR,32) + +/* Write access macros for general use */ +#define MCF5272_WR_DMA_DCMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_DMA_DCMR,32,DATA) +#define MCF5272_WR_DMA_DCIR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_DMA_DCIR,16,DATA) +#define MCF5272_WR_DMA_DBCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_DMA_DBCR,32,DATA) +#define MCF5272_WR_DMA_DSAR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_DMA_DSAR,32,DATA) +#define MCF5272_WR_DMA_DDAR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_DMA_DDAR,32,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_DMA_DCMR_RESET (0x80000000) +#define MCF5272_DMA_DCMR_EN (0x40000000) +#define MCF5272_DMA_DCMR_RQM (0x000C0000) +#define MCF5272_DMA_DCMR_DSTM_INC (0x00002000) +#define MCF5272_DMA_DCMR_DSTT_UD (0x00000400) +#define MCF5272_DMA_DCMR_DSTT_UC (0x00000800) +#define MCF5272_DMA_DCMR_DSTT_SD (0x00001400) +#define MCF5272_DMA_DCMR_DSTT_SC (0x00001800) +#define MCF5272_DMA_DCMR_DSTS_LW (0x00000000) +#define MCF5272_DMA_DCMR_DSTS_B (0x00000100) +#define MCF5272_DMA_DCMR_DSTS_W (0x00000200) +#define MCF5272_DMA_DCMR_DSTS_LINE (0x00000300) +#define MCF5272_DMA_DCMR_SRCM_INC (0x00000020) +#define MCF5272_DMA_DCMR_SRCT_UD (0x00000004) +#define MCF5272_DMA_DCMR_SRCT_UC (0x00000008) +#define MCF5272_DMA_DCMR_SRCT_SD (0x00000014) +#define MCF5272_DMA_DCMR_SRCT_SC (0x00000018) +#define MCF5272_DMA_DCMR_SRCS_LW (0x00000000) +#define MCF5272_DMA_DCMR_SRCS_B (0x00000001) +#define MCF5272_DMA_DCMR_SRCS_W (0x00000002) +#define MCF5272_DMA_DCMR_SRCS_LINE (0x00000003) +#define MCF5272_DMA_DCIR_INVEN (0x1000) +#define MCF5272_DMA_DCIR_ASCEN (0x0800) +#define MCF5272_DMA_DCIR_TEEN (0x0200) +#define MCF5272_DMA_DCIR_TCEN (0x0100) +#define MCF5272_DMA_DCIR_INV (0x0010) +#define MCF5272_DMA_DCIR_ASC (0x0008) +#define MCF5272_DMA_DCIR_TE (0x0002) +#define MCF5272_DMA_DCIR_TC (0x0001) + +/********************************************************************** +* +* USART Module Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_UART0_UMR (0x0100) /* RW */ +#define MCF5272_UART0_USR (0x0104) /* USR RO, UCSR WO */ +#define MCF5272_UART0_UCR (0x0108) /* WO */ +#define MCF5272_UART0_UBUF (0x010C) /* URB RO, UTB WO */ +#define MCF5272_UART0_UCCR (0x0110) /* UCCR RO, UACR WO */ +#define MCF5272_UART0_UISR (0x0114) /* UISR RO, UIMR WO */ +#define MCF5272_UART0_UBG1 (0x0118) /* WO */ +#define MCF5272_UART0_UBG2 (0x011C) /* WO */ +#define MCF5272_UART0_UABR1 (0x0120) /* RO */ +#define MCF5272_UART0_UABR2 (0x0124) /* RO */ +#define MCF5272_UART0_UTFCSR (0x0128) /* RW */ +#define MCF5272_UART0_URFCSR (0x012C) /* RW */ +#define MCF5272_UART0_UIP (0x0134) /* RO */ +#define MCF5272_UART0_UOP1 (0x0138) /* WO */ +#define MCF5272_UART0_UOP0 (0x013C) /* WO */ + +#define MCF5272_UART1_UMR (0x0140) /* RW */ +#define MCF5272_UART1_USR (0x0144) /* USR RO, UCSR WO */ +#define MCF5272_UART1_UCR (0x0148) /* WO */ +#define MCF5272_UART1_UBUF (0x014C) /* URB RO, UTB WO */ +#define MCF5272_UART1_UCCR (0x0150) /* UCCR RO, UACR WO */ +#define MCF5272_UART1_UISR (0x0154) /* UISR RO, UIMR WO */ +#define MCF5272_UART1_UBG1 (0x0158) /* WO */ +#define MCF5272_UART1_UBG2 (0x015C) /* WO */ +#define MCF5272_UART1_UABR1 (0x0160) /* RO */ +#define MCF5272_UART1_UABR2 (0x0164) /* RO */ +#define MCF5272_UART1_UTFCSR (0x0168) /* RW */ +#define MCF5272_UART1_URFCSR (0x016C) /* RW */ +#define MCF5272_UART1_UIP (0x0174) /* RO */ +#define MCF5272_UART1_UOP1 (0x0178) /* WO */ +#define MCF5272_UART1_UOP0 (0x017C) /* WO */ + +/* Read access macros for general use */ +#define MCF5272_RD_UART0_UMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_UMR,8) +#define MCF5272_RD_UART0_USR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_USR,8) +#define MCF5272_RD_UART0_URB(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_UBUF,8) +#define MCF5272_RD_UART0_UCCR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_UCCR,8) +#define MCF5272_RD_UART0_UISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_UISR,8) +#define MCF5272_RD_UART0_UABR1(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_UABR1,8) +#define MCF5272_RD_UART0_UABR2(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UABR2,8) +#define MCF5272_RD_UART0_UTFCSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_UTFCSR,8) +#define MCF5272_RD_UART0_URFCSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_URFCSR,8) +#define MCF5272_RD_UART0_UIP(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART0_UIP,8) + +#define MCF5272_RD_UART1_UMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UMR,8) +#define MCF5272_RD_UART1_USR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_USR,8) +#define MCF5272_RD_UART1_URB(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UBUF,8) +#define MCF5272_RD_UART1_UCCR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UCCR,8) +#define MCF5272_RD_UART1_UISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UISR,8) +#define MCF5272_RD_UART1_UABR1(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UABR1,8) +#define MCF5272_RD_UART1_UABR2(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UABR2,8) +#define MCF5272_RD_UART1_UTFCSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UTFCSR,8) +#define MCF5272_RD_UART1_URFCSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_URFCSR,8) +#define MCF5272_RD_UART1_UIP(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_UART1_UIP,8) + +/* Write access macros for general use */ +#define MCF5272_WR_UART0_UMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UMR,8,DATA) +#define MCF5272_WR_UART0_UCSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_USR,8,DATA) +#define MCF5272_WR_UART0_UCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UCR,8,DATA) +#define MCF5272_WR_UART0_UTB(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UBUF,8,DATA) +#define MCF5272_WR_UART0_UACR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UCCR,8,DATA) +#define MCF5272_WR_UART0_UIMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UISR,8,DATA) +#define MCF5272_WR_UART0_UBG1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UBG1,8,DATA) +#define MCF5272_WR_UART0_UBG2(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UBG2,8,DATA) +#define MCF5272_WR_UART0_UTFCSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UTFCSR,8,DATA) +#define MCF5272_WR_UART0_URFCSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_URFCSR,8,DATA) +#define MCF5272_WR_UART0_UOP1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UOP1,8,DATA) +#define MCF5272_WR_UART0_UOP0(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART0_UOP0,8,DATA) + +#define MCF5272_WR_UART1_UMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UMR,8,DATA) +#define MCF5272_WR_UART1_UCSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_USR,8,DATA) +#define MCF5272_WR_UART1_UCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UCR,8,DATA) +#define MCF5272_WR_UART1_UTB(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UBUF,8,DATA) +#define MCF5272_WR_UART1_UACR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UCCR,8,DATA) +#define MCF5272_WR_UART1_UIMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UISR,8,DATA) +#define MCF5272_WR_UART1_UBG1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UBG1,8,DATA) +#define MCF5272_WR_UART1_UBG2(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UBG2,8,DATA) +#define MCF5272_WR_UART1_UTFCSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UTFCSR,8,DATA) +#define MCF5272_WR_UART1_URFCSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_URFCSR,8,DATA) +#define MCF5272_WR_UART1_UOP1(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UOP1,8,DATA) +#define MCF5272_WR_UART1_UOP0(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_UART1_UOP0,8,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_UART_UMR1_RXRTS (0x80) +#define MCF5272_UART_UMR1_RXIRQ (0x40) +#define MCF5272_UART_UMR1_ERR (0x20) +#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C) +#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18) +#define MCF5272_UART_UMR1_PM_NONE (0x10) +#define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C) +#define MCF5272_UART_UMR1_PM_FORCE_LO (0x08) +#define MCF5272_UART_UMR1_PM_ODD (0x04) +#define MCF5272_UART_UMR1_PM_EVEN (0x00) +#define MCF5272_UART_UMR1_BC_5 (0x00) +#define MCF5272_UART_UMR1_BC_6 (0x01) +#define MCF5272_UART_UMR1_BC_7 (0x02) +#define MCF5272_UART_UMR1_BC_8 (0x03) + +#define MCF5272_UART_UMR2_CM_NORMAL (0x00) +#define MCF5272_UART_UMR2_CM_ECHO (0x40) +#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80) +#define MCF5272_UART_UMR2_CM_REMOTE_LOOP (0xC0) +#define MCF5272_UART_UMR2_TXRTS (0x20) +#define MCF5272_UART_UMR2_TXCTS (0x10) +#define MCF5272_UART_UMR2_STOP_BITS_1 (0x07) +#define MCF5272_UART_UMR2_STOP_BITS_15 (0x08) +#define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F) +#define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */ + +#define MCF5272_UART_USR_RB (0x80) +#define MCF5272_UART_USR_FE (0x40) +#define MCF5272_UART_USR_PE (0x20) +#define MCF5272_UART_USR_OE (0x10) +#define MCF5272_UART_USR_TXEMP (0x08) +#define MCF5272_UART_USR_TXRDY (0x04) +#define MCF5272_UART_USR_FFULL (0x02) +#define MCF5272_UART_USR_RXRDY (0x01) + +#define MCF5272_UART_UCSR_RCS(a) (((a)&0x0f)<<4) /* Rx Clk Select */ +#define MCF5272_UART_UCSR_TCS(a) ((a)&0x0f) /* Tx Clk Select */ + + +#define MCF5272_UART_UCR_NONE (0x00) +#define MCF5272_UART_UCR_STOP_BREAK (0x70) +#define MCF5272_UART_UCR_START_BREAK (0x60) +#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF5272_UART_UCR_RESET_ERROR (0x40) +#define MCF5272_UART_UCR_RESET_TX (0x30) +#define MCF5272_UART_UCR_RESET_RX (0x20) +#define MCF5272_UART_UCR_RESET_MR (0x10) +#define MCF5272_UART_UCR_TX_DISABLED (0x08) +#define MCF5272_UART_UCR_TX_ENABLED (0x04) +#define MCF5272_UART_UCR_RX_DISABLED (0x02) +#define MCF5272_UART_UCR_RX_ENABLED (0x01) + +#define MCF5272_UART_UCCR_COS (0x10) +#define MCF5272_UART_UCCR_CTS (0x01) + +#define MCF5272_UART_UACR_BRG (0x80) +#define MCF5272_UART_UACR_CTMS_TIMER (0x60) +#define MCF5272_UART_UACR_IEC (0x01) + +#define MCF5272_UART_UISR_COS (0x80) +#define MCF5272_UART_UISR_DB (0x04) +#define MCF5272_UART_UISR_RXRDY (0x02) +#define MCF5272_UART_UISR_TXRDY (0x01) + +#define MCF5272_UART_UIMR_COS (0x80) +#define MCF5272_UART_UIMR_DB (0x04) +#define MCF5272_UART_UIMR_FFULL (0x02) +#define MCF5272_UART_UIMR_TXRDY (0x01) + + +/********************************************************************** +* +* SDRAM Controller Module Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_SDRAMC_SDCCR (0x0180) +#define MCF5272_SDRAMC_SDCTR (0x0184) + +/* Read access macros for general use */ +#define MCF5272_RD_SDRAMC_SDCCR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_SDRAMC_SDCCR,32) +#define MCF5272_RD_SDRAMC_SDCTR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_SDRAMC_SDCTR,32) + +/* Write access macros for general use */ +#define MCF5272_WR_SDRAMC_SDCCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SDRAMC_SDCCR,32,DATA) +#define MCF5272_WR_SDRAMC_SDCTR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_SDRAMC_SDCTR,32,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_SDRAMC_SDCCR_MCAS_A7 (0x0 << 13) +#define MCF5272_SDRAMC_SDCCR_MCAS_A8 (0x1 << 13) +#define MCF5272_SDRAMC_SDCCR_MCAS_A9 (0x2 << 13) +#define MCF5272_SDRAMC_SDCCR_MCAS_A10 (0x3 << 13) +#define MCF5272_SDRAMC_SDCCR_BALOC_A19 (0x0 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A20 (0x1 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A21 (0x2 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A22 (0x3 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A23 (0x4 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A24 (0x5 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A25 (0x6 << 8) +#define MCF5272_SDRAMC_SDCCR_BALOC_A26 (0x7 << 8) +#define MCF5272_SDRAMC_SDCCR_GSL (0x00000080) +#define MCF5272_SDRAMC_SDCCR_REG (0x00000010) +#define MCF5272_SDRAMC_SDCCR_INV (0x00000008) +#define MCF5272_SDRAMC_SDCCR_SLEEP (0x00000004) +#define MCF5272_SDRAMC_SDCCR_ACT (0x00000002) +#define MCF5272_SDRAMC_SDCCR_INIT (0x00000001) + +#define MCF5272_SDRAMC_SDCTR_RTP_66MHz (0x3D << 10) +#define MCF5272_SDRAMC_SDCTR_RTP_48MHz (0x2B << 10) +#define MCF5272_SDRAMC_SDCTR_RTP_33MHz (0x1D << 10) +#define MCF5272_SDRAMC_SDCTR_RTP_25MHz (0x16 << 10) +#define MCF5272_SDRAMC_SDCTR_RC(x) ((x & 0x3) << 8) +#define MCF5272_SDRAMC_SDCTR_RP(x) ((x & 0x3) << 4) +#define MCF5272_SDRAMC_SDCTR_RCD(x) ((x & 0x3) << 2) +#define MCF5272_SDRAMC_SDCTR_CLT_2 (0x00000001) +#define MCF5272_SDRAMC_SDCTR_CLT_3 (0x00000002) +#define MCF5272_SDRAMC_SDCTR_CLT_4 (0x00000003) + +/********************************************************************** +* +* Timer Module Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_TIMER0_TMR (0x0200) +#define MCF5272_TIMER0_TRR (0x0204) +#define MCF5272_TIMER0_TCR (0x0208) +#define MCF5272_TIMER0_TCN (0x020C) +#define MCF5272_TIMER0_TER (0x0210) +#define MCF5272_TIMER1_TMR (0x0220) +#define MCF5272_TIMER1_TRR (0x0224) +#define MCF5272_TIMER1_TCR (0x0228) +#define MCF5272_TIMER1_TCN (0x022C) +#define MCF5272_TIMER1_TER (0x0230) +#define MCF5272_TIMER2_TMR (0x0240) +#define MCF5272_TIMER2_TRR (0x0244) +#define MCF5272_TIMER2_TCR (0x0248) +#define MCF5272_TIMER2_TCN (0x024C) +#define MCF5272_TIMER2_TER (0x0250) +#define MCF5272_TIMER3_TMR (0x0260) +#define MCF5272_TIMER3_TRR (0x0264) +#define MCF5272_TIMER3_TCR (0x0268) +#define MCF5272_TIMER3_TCN (0x026C) +#define MCF5272_TIMER3_TER (0x0270) +#define MCF5272_TIMER_WRRR (0x0280) +#define MCF5272_TIMER_WIRR (0x0284) +#define MCF5272_TIMER_WCR (0x0288) +#define MCF5272_TIMER_WER (0x028C) + +/* Read access macros for general use */ +#define MCF5272_RD_TIMER0_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TMR,16) +#define MCF5272_RD_TIMER0_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TRR,16) +#define MCF5272_RD_TIMER0_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TCR,16) +#define MCF5272_RD_TIMER0_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TCN,16) +#define MCF5272_RD_TIMER0_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TER,16) + +#define MCF5272_RD_TIMER1_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TMR,16) +#define MCF5272_RD_TIMER1_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TRR,16) +#define MCF5272_RD_TIMER1_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TCR,16) +#define MCF5272_RD_TIMER1_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TCN,16) +#define MCF5272_RD_TIMER1_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TER,16) + +#define MCF5272_RD_TIMER2_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TMR,16) +#define MCF5272_RD_TIMER2_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TRR,16) +#define MCF5272_RD_TIMER2_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TCR,16) +#define MCF5272_RD_TIMER2_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TCN,16) +#define MCF5272_RD_TIMER2_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TER,16) + +#define MCF5272_RD_TIMER3_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TMR,16) +#define MCF5272_RD_TIMER3_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TRR,16) +#define MCF5272_RD_TIMER3_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TCR,16) +#define MCF5272_RD_TIMER3_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TCN,16) +#define MCF5272_RD_TIMER3_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TER,16) + +#define MCF5272_RD_TIMER_TMR(IMMP,NUM) \ +Mcf5272_iord(IMMP,MCF5272_TIMER0_TMR + (NUM * 0x20),16) +#define MCF5272_RD_TIMER_TRR(IMMP,NUM) \ +Mcf5272_iord(IMMP,MCF5272_TIMER0_TRR + (NUM * 0x20),16) +#define MCF5272_RD_TIMER_TCR(IMMP,NUM) \ +Mcf5272_iord(IMMP,MCF5272_TIMER0_TCR + (NUM * 0x20),16) +#define MCF5272_RD_TIMER_TCN(IMMP,NUM) \ +Mcf5272_iord(IMMP,MCF5272_TIMER0_TCN + (NUM * 0x20),16) +#define MCF5272_RD_TIMER_TER(IMMP,NUM) \ +Mcf5272_iord(IMMP,MCF5272_TIMER0_TER + (NUM * 0x20),16) + +#define MCF5272_RD_TIMER_WRRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WRRR,16) +#define MCF5272_RD_TIMER_WIRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WIRR,16) +#define MCF5272_RD_TIMER_WCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WCR,16) +#define MCF5272_RD_TIMER_WER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WER,16) + +/* Write access macros for general use */ +#define MCF5272_WR_TIMER0_TMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TMR,16,DATA) +#define MCF5272_WR_TIMER0_TRR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TRR,16,DATA) +#define MCF5272_WR_TIMER0_TCN(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TCN,16,DATA) +#define MCF5272_WR_TIMER0_TER(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TER,16,DATA) +#define MCF5272_WR_TIMER1_TMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER1_TMR,16,DATA) +#define MCF5272_WR_TIMER1_TRR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER1_TRR,16,DATA) +#define MCF5272_WR_TIMER1_TCN(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER1_TCN,16,DATA) +#define MCF5272_WR_TIMER1_TER(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER1_TER,16,DATA) +#define MCF5272_WR_TIMER2_TMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER2_TMR,16,DATA) +#define MCF5272_WR_TIMER2_TRR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER2_TRR,16,DATA) +#define MCF5272_WR_TIMER2_TCN(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER2_TCN,16,DATA) +#define MCF5272_WR_TIMER2_TER(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER2_TER,16,DATA) +#define MCF5272_WR_TIMER3_TMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER3_TMR,16,DATA) +#define MCF5272_WR_TIMER3_TRR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER3_TRR,16,DATA) +#define MCF5272_WR_TIMER3_TCN(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER3_TCN,16,DATA) +#define MCF5272_WR_TIMER3_TER(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER3_TER,16,DATA) +#define MCF5272_WR_TIMER_WRRR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER_WRRR,16,DATA) +#define MCF5272_WR_TIMER_WIRR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER_WIRR,16,DATA) +#define MCF5272_WR_TIMER_WCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER_WCR,16,DATA) +#define MCF5272_WR_TIMER_WER(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER_WER,16,DATA) + +#define MCF5272_WR_TIMER_TMR(IMMP,NUM,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TMR + (NUM * 0x20),16,DATA) +#define MCF5272_WR_TIMER_TRR(IMMP,NUM,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TRR + (NUM * 0x20),16,DATA) +#define MCF5272_WR_TIMER_TCN(IMMP,NUM,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TCN + (NUM * 0x20),16,DATA) +#define MCF5272_WR_TIMER_TER(IMMP,NUM,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_TIMER0_TER + (NUM * 0x20),16,DATA) + +/* Bit level definitions and macros */ +#define MCF5272_TIMER_TMR_PS(a) (((a)&0x00FF)<<8) +#define MCF5272_TIMER_TMR_CE_ANY (0x00C0) +#define MCF5272_TIMER_TMR_CE_RISE (0x0080) +#define MCF5272_TIMER_TMR_CE_FALL (0x0040) +#define MCF5272_TIMER_TMR_CE_NONE (0x0000) +#define MCF5272_TIMER_TMR_OM (0x0020) +#define MCF5272_TIMER_TMR_ORI (0x0010) +#define MCF5272_TIMER_TMR_FRR (0x0008) +#define MCF5272_TIMER_TMR_CLK_TIN (0x0006) +#define MCF5272_TIMER_TMR_CLK_DIV16 (0x0004) +#define MCF5272_TIMER_TMR_CLK_MSCLK (0x0002) +#define MCF5272_TIMER_TMR_CLK_STOP (0x0000) +#define MCF5272_TIMER_TMR_RST (0x0001) + +#define MCF5272_TIMER_TER_REF (0x02) +#define MCF5272_TIMER_TER_CAP (0x01) + +/********************************************************************** +* +* PLI Module Registers Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_PLI_P0B1RR (0x0300) +#define MCF5272_PLI_P1B1RR (0x0304) +#define MCF5272_PLI_P2B1RR (0x0308) +#define MCF5272_PLI_P3B1RR (0x030C) +#define MCF5272_PLI_P0B2RR (0x0310) +#define MCF5272_PLI_P1B2RR (0x0314) +#define MCF5272_PLI_P2B2RR (0x0318) +#define MCF5272_PLI_P3B2RR (0x031C) +#define MCF5272_PLI_P0DRR (0x0320) +#define MCF5272_PLI_P1DRR (0x0321) +#define MCF5272_PLI_P2DRR (0x0322) +#define MCF5272_PLI_P3DRR (0x0323) +#define MCF5272_PLI_P0B1TR (0x0328) +#define MCF5272_PLI_P1B1TR (0x032C) +#define MCF5272_PLI_P2B1TR (0x0330) +#define MCF5272_PLI_P3B1TR (0x0334) +#define MCF5272_PLI_P0B2TR (0x0338) +#define MCF5272_PLI_P1B2TR (0x033C) +#define MCF5272_PLI_P2B2TR (0x0340) +#define MCF5272_PLI_P3B2TR (0x0344) +#define MCF5272_PLI_P0DTR (0x0348) +#define MCF5272_PLI_P1DTR (0x0349) +#define MCF5272_PLI_P2DTR (0x034A) +#define MCF5272_PLI_P3DTR (0x034B) +#define MCF5272_PLI_P0CR (0x0350) +#define MCF5272_PLI_P1CR (0x0352) +#define MCF5272_PLI_P2CR (0x0354) +#define MCF5272_PLI_P3CR (0x0356) +#define MCF5272_PLI_P0ICR (0x0358) +#define MCF5272_PLI_P1ICR (0x035A) +#define MCF5272_PLI_P2ICR (0x035C) +#define MCF5272_PLI_P3ICR (0x035E) +#define MCF5272_PLI_P0GMR (0x0360) +#define MCF5272_PLI_P1GMR (0x0362) +#define MCF5272_PLI_P2GMR (0x0364) +#define MCF5272_PLI_P3GMR (0x0366) +#define MCF5272_PLI_P0GMT (0x0368) +#define MCF5272_PLI_P1GMT (0x036A) +#define MCF5272_PLI_P2GMT (0x036C) +#define MCF5272_PLI_P3GMT (0x036E) +#define MCF5272_PLI_PGMTS (0x0371) +#define MCF5272_PLI_PGMTA (0x0372) +#define MCF5272_PLI_P0GCIR (0x0374) +#define MCF5272_PLI_P1GCIR (0x0375) +#define MCF5272_PLI_P2GCIR (0x0376) +#define MCF5272_PLI_P3GCIR (0x0377) +#define MCF5272_PLI_P0GCIT (0x0378) +#define MCF5272_PLI_P1GCIT (0x0379) +#define MCF5272_PLI_P2GCIT (0x037A) +#define MCF5272_PLI_P3GCIT (0x037E) +#define MCF5272_PLI_PGCITSR (0x037F) +#define MCF5272_PLI_PDSUSR (0x0382) +#define MCF5272_PLI_PDCSR (0x0383) +#define MCF5272_PLI_P0PSR (0x0384) +#define MCF5272_PLI_P1PSR (0x0386) +#define MCF5272_PLI_P2PSR (0x0388) +#define MCF5272_PLI_P3PSR (0x038A) +#define MCF5272_PLI_PASR (0x038C) +#define MCF5272_PLI_PLCR (0x038F) +#define MCF5272_PLI_PDRQR (0x0392) +#define MCF5272_PLI_P0SDR (0x0394) +#define MCF5272_PLI_P1SDR (0x0396) +#define MCF5272_PLI_P2SDR (0x0398) +#define MCF5272_PLI_P3SDR (0x039A) +#define MCF5272_PLI_PCKSELR (0x039E) + +/* Read access macros for general use */ +#define MCF5272_RD_PLI_P0B1RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0B1RR,32) +#define MCF5272_RD_PLI_P1B1RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1B1RR,32) +#define MCF5272_RD_PLI_P2B1RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2B1RR,32) +#define MCF5272_RD_PLI_P3B1RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3B1RR,32) +#define MCF5272_RD_PLI_P0B2RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0B2RR,32) +#define MCF5272_RD_PLI_P1B2RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1B2RR,32) +#define MCF5272_RD_PLI_P2B2RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2B2RR,32) +#define MCF5272_RD_PLI_P3B2RR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3B2RR,32) +#define MCF5272_RD_PLI_P0DRR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0DRR,8) +#define MCF5272_RD_PLI_P1DRR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1DRR,8) +#define MCF5272_RD_PLI_P2DRR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2DRR,8) +#define MCF5272_RD_PLI_P3DRR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3DRR,8) +#define MCF5272_RD_PLI_P0B1TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0B1TR,32) +#define MCF5272_RD_PLI_P1B1TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1B1TR,32) +#define MCF5272_RD_PLI_P2B1TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2B1TR,32) +#define MCF5272_RD_PLI_P3B1TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3B1TR,32) +#define MCF5272_RD_PLI_P0B2TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0B2TR,32) +#define MCF5272_RD_PLI_P1B2TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1B2TR,32) +#define MCF5272_RD_PLI_P2B2TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2B2TR,32) +#define MCF5272_RD_PLI_P3B2TR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3B2TR,32) +#define MCF5272_RD_PLI_P0DTR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0DTR,8) +#define MCF5272_RD_PLI_P1DTR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1DTR,8) +#define MCF5272_RD_PLI_P2DTR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2DTR,8) +#define MCF5272_RD_PLI_P3DTR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3DTR,8) +#define MCF5272_RD_PLI_P0CR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0CR,16) +#define MCF5272_RD_PLI_P1CR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1CR,16) +#define MCF5272_RD_PLI_P2CR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2CR,16) +#define MCF5272_RD_PLI_P3CR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3CR,16) +#define MCF5272_RD_PLI_P0ICR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0ICR,16) +#define MCF5272_RD_PLI_P1ICR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1ICR,16) +#define MCF5272_RD_PLI_P2ICR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2ICR,16) +#define MCF5272_RD_PLI_P3ICR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3ICR,16) +#define MCF5272_RD_PLI_P0GMR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0GMR,16) +#define MCF5272_RD_PLI_P1GMR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1GMR,16) +#define MCF5272_RD_PLI_P2GMR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2GMR,16) +#define MCF5272_RD_PLI_P3GMR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3GMR,16) +#define MCF5272_RD_PLI_P0GMT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0GMT,16) +#define MCF5272_RD_PLI_P1GMT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1GMT,16) +#define MCF5272_RD_PLI_P2GMT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2GMT,16) +#define MCF5272_RD_PLI_P3GMT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3GMT,16) +#define MCF5272_RD_PLI_PGMTS(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PGMTS,8) +#define MCF5272_RD_PLI_PGMTA(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PGMTA,8) +#define MCF5272_RD_PLI_P0GCIR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0GCIR,8) +#define MCF5272_RD_PLI_P1GCIR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1GCIR,8) +#define MCF5272_RD_PLI_P2GCIR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2GCIR,8) +#define MCF5272_RD_PLI_P3GCIR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3GCIR,8) +#define MCF5272_RD_PLI_P0GCIT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0GCIT,8) +#define MCF5272_RD_PLI_P1GCIT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1GCIT,8) +#define MCF5272_RD_PLI_P2GCIT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2GCIT,8) +#define MCF5272_RD_PLI_P3GCIT(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3GCIT,8) +#define MCF5272_RD_PLI_PGCITSR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PGCITSR,8) +#define MCF5272_RD_PLI_PDSUSR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PDSUSR,8) +#define MCF5272_RD_PLI_PDCSR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PDCSR,8) +#define MCF5272_RD_PLI_P0PSR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0PSR,16) +#define MCF5272_RD_PLI_P1PSR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1PSR,16) +#define MCF5272_RD_PLI_P2PSR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2PSR,16) +#define MCF5272_RD_PLI_P3PSR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3PSR,16) +#define MCF5272_RD_PLI_PASR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PASR,16) +#define MCF5272_RD_PLI_PLCR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PLCR,8) +#define MCF5272_RD_PLI_PDRQR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PDRQR,16) +#define MCF5272_RD_PLI_P0SDR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P0SDR,16) +#define MCF5272_RD_PLI_P1SDR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P1SDR,16) +#define MCF5272_RD_PLI_P2SDR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P2SDR,16) +#define MCF5272_RD_PLI_P3SDR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_P3SDR,16) +#define MCF5272_RD_PLI_PCKSELR(IMMP) Mcf5272_iord(IMMP,MCF5272_PLI_PCKSELR,16) + +/* Write access macros for general use */ +#define MCF5272_WR_PLI_P0B1TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0B1TR,32,DATA) +#define MCF5272_WR_PLI_P1B1TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1B1TR,32,DATA) +#define MCF5272_WR_PLI_P2B1TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2B1TR,32,DATA) +#define MCF5272_WR_PLI_P3B1TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3B1TR,32,DATA) +#define MCF5272_WR_PLI_P0B2TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0B2TR,32,DATA) +#define MCF5272_WR_PLI_P1B2TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1B2TR,32,DATA) +#define MCF5272_WR_PLI_P2B2TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2B2TR,32,DATA) +#define MCF5272_WR_PLI_P3B2TR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3B2TR,32,DATA) +#define MCF5272_WR_PLI_P0DTR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0DTR,8,DATA) +#define MCF5272_WR_PLI_P1DTR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1DTR,8,DATA) +#define MCF5272_WR_PLI_P2DTR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2DTR,8,DATA) +#define MCF5272_WR_PLI_P3DTR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3DTR,8,DATA) +#define MCF5272_WR_PLI_P0CR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0CR,16,DATA) +#define MCF5272_WR_PLI_P1CR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1CR,16,DATA) +#define MCF5272_WR_PLI_P2CR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2CR,16,DATA) +#define MCF5272_WR_PLI_P3CR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3CR,16,DATA) +#define MCF5272_WR_PLI_P0ICR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0ICR,16,DATA) +#define MCF5272_WR_PLI_P1ICR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1ICR,16,DATA) +#define MCF5272_WR_PLI_P2ICR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2ICR,16,DATA) +#define MCF5272_WR_PLI_P3ICR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3ICR,16,DATA) +#define MCF5272_WR_PLI_P0GMT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0GMR,16,DATA) +#define MCF5272_WR_PLI_P1GMT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1GMT,16,DATA) +#define MCF5272_WR_PLI_P2GMT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2GMT,16,DATA) +#define MCF5272_WR_PLI_P3GMT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3GMT,16,DATA) +#define MCF5272_WR_PLI_PGMTA(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_PGMTA,8,DATA) +#define MCF5272_WR_PLI_P0GCIT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0GCIT,8,DATA) +#define MCF5272_WR_PLI_P1GCIT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1GCIT,8,DATA) +#define MCF5272_WR_PLI_P2GCIT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2GCIT,8,DATA) +#define MCF5272_WR_PLI_P3GCIT(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3GCIT,8,DATA) +#define MCF5272_WR_PLI_PLCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_PLCR,8,DATA) +#define MCF5272_WR_PLI_PDRQR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_PDRQR,16,DATA) +#define MCF5272_WR_PLI_P0SDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P0SDR,16,DATA) +#define MCF5272_WR_PLI_P1SDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P1SDR,16,DATA) +#define MCF5272_WR_PLI_P2SDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P2SDR,16,DATA) +#define MCF5272_WR_PLI_P3SDR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_P3SDR,16,DATA) +#define MCF5272_WR_PLI_PCKSELR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_PLI_PCKSELR,16,DATA) + + +/********************************************************************** +* +* Fast Ethernet Controller Module Register Descriptions +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_FEC_ECR (0x0840) +#define MCF5272_FEC_EIR (0x0844) +#define MCF5272_FEC_IMR (0x0848) +#define MCF5272_FEC_IVSR (0x084C) +#define MCF5272_FEC_RDAR (0x0850) +#define MCF5272_FEC_TDAR (0x0854) +#define MCF5272_FEC_MMFR (0x0880) +#define MCF5272_FEC_MSCR (0x0884) +#define MCF5272_FEC_FRBR (0x08CC) +#define MCF5272_FEC_FRSR (0x08D0) +#define MCF5272_FEC_TFWR (0x08E4) +#define MCF5272_FEC_FTSR (0x08EC) +#define MCF5272_FEC_RCR (0x0944) +#define MCF5272_FEC_MFLR (0x0948) +#define MCF5272_FEC_TCR (0x0984) +#define MCF5272_FEC_MALR (0x0C00) +#define MCF5272_FEC_MAUR (0x0C04) +#define MCF5272_FEC_HTUR (0x0C08) +#define MCF5272_FEC_HTLR (0x0C0C) +#define MCF5272_FEC_ERDSR (0x0C10) +#define MCF5272_FEC_ETDSR (0x0C14) +#define MCF5272_FEC_EMRBR (0x0C18) +#define MCF5272_FEC_EFIFO (0x0C40) /* 0x0C40 - 0x0DFF */ + +/* Read access macros for general use */ +#define MCF5272_RD_FEC_ECR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_ECR,32) +#define MCF5272_RD_FEC_EIR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_EIR,32) +#define MCF5272_RD_FEC_IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_IMR,32) +#define MCF5272_RD_FEC_IVSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_IVSR,32) +#define MCF5272_RD_FEC_RDAR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_RDAR,32) +#define MCF5272_RD_FEC_TDAR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_TDAR,32) +#define MCF5272_RD_FEC_MMFR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_MMFR,32) +#define MCF5272_RD_FEC_MSCR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_MSCR,32) +#define MCF5272_RD_FEC_FRBR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_FRBR,32) +#define MCF5272_RD_FEC_FRSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_FRSR,32) +#define MCF5272_RD_FEC_TFWR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_TFWR,32) +#define MCF5272_RD_FEC_FTSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_FTSR,32) +#define MCF5272_RD_FEC_RCR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_RCR,32) +#define MCF5272_RD_FEC_MFLR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_MFLR,32) +#define MCF5272_RD_FEC_TCR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_TCR,32) +#define MCF5272_RD_FEC_MALR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_MALR,32) +#define MCF5272_RD_FEC_MAUR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_MAUR,32) +#define MCF5272_RD_FEC_HTUR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_HTUR,32) +#define MCF5272_RD_FEC_HTLR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_HTLR,32) +#define MCF5272_RD_FEC_ERDSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_ERDSR,32) +#define MCF5272_RD_FEC_ETDSR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_ETDSR,32) +#define MCF5272_RD_FEC_EMRBR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_FEC_EMRBR,32) + +/* Write access macros for general use */ +#define MCF5272_WR_FEC_ECR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_ECR,32,DATA) +#define MCF5272_WR_FEC_EIR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_EIR,32,DATA) +#define MCF5272_WR_FEC_IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_IMR,32,DATA) +#define MCF5272_WR_FEC_RDAR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_RDAR,32,DATA) +#define MCF5272_WR_FEC_TDAR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_TDAR,32,DATA) +#define MCF5272_WR_FEC_MMFR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_MMFR,32,DATA) +#define MCF5272_WR_FEC_MSCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_MSCR,32,DATA) +#define MCF5272_WR_FEC_FRSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_FRSR,32,DATA) +#define MCF5272_WR_FEC_TFWR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_TFWR,32,DATA) +#define MCF5272_WR_FEC_FTSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_FTSR,32,DATA) +#define MCF5272_WR_FEC_RCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_RCR,32,DATA) +#define MCF5272_WR_FEC_MFLR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_MFLR,32,DATA) +#define MCF5272_WR_FEC_TCR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_TCR,32,DATA) +#define MCF5272_WR_FEC_MALR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_MALR,32,DATA) +#define MCF5272_WR_FEC_MAUR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_MAUR,32,DATA) +#define MCF5272_WR_FEC_HTUR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_HTUR,32,DATA) +#define MCF5272_WR_FEC_HTLR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_HTLR,32,DATA) +#define MCF5272_WR_FEC_ERDSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_ERDSR,32,DATA) +#define MCF5272_WR_FEC_ETDSR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_ETDSR,32,DATA) +#define MCF5272_WR_FEC_EMRBR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_FEC_EMRBR,32,DATA) + + +/* Bit level definitions and macros */ +#define MCF5272_FEC_ECR_RESET (0x00000001) +#define MCF5272_FEC_ECR_ETHER_EN (0x00000002) +#define MCF5272_FEC_EIR_GRA (0x10000000) +#define MCF5272_FEC_EIR_RXF (0x02000000) +#define MCF5272_FEC_EIR_TXF (0x08000000) +#define MCF5272_FEC_IMR_HBEEN (0x80000000) +#define MCF5272_FEC_IMR_BREN (0x40000000) +#define MCF5272_FEC_IMR_BTEN (0x20000000) +#define MCF5272_FEC_IMR_GRAEN (0x10000000) +#define MCF5272_FEC_IMR_TXFEN (0x08000000) +#define MCF5272_FEC_IMR_TXBEN (0x04000000) +#define MCF5272_FEC_IMR_RXFEN (0x02000000) +#define MCF5272_FEC_IMR_RXBEN (0x01000000) +#define MCF5272_FEC_IMR_MIIEN (0x00800000) +#define MCF5272_FEC_IMR_EBERREN (0x00400000) +#define MCF5272_FEC_RCR_PROM (0x00000008) +#define MCF5272_FEC_RCR_MII_MODE (0x00000004) +#define MCF5272_FEC_RCR_DRT (0x00000002) +#define MCF5272_FEC_RCR_LOOP (0x00000001) +#define MCF5272_FEC_TCR_GTS (0x00000001) +#define MCF5272_FEC_TCR_HBC (0x00000002) +#define MCF5272_FEC_TCR_FDEN (0x00000004) +#define MCF5272_MMFR_MODE (0x00004000) +#define MCF5272_MMFR_DUPLEX (0x00000200) +#define MCF5272_MMFR_LOOP (0x00004000) +#define MCF5272_MMFR_NEGOTIATE (0x00001000) +#define MCF5272_MMFR_100 (0x00002000) + + +/* + * Bit level Buffer Descriptor definitions + */ + +#define MCF5272_FEC_TX_BD_R 0x8000 +#define MCF5272_FEC_TX_BD_INUSE 0x4000 +#define MCF5272_FEC_TX_BD_TO1 0x4000 +#define MCF5272_FEC_TX_BD_W 0x2000 +#define MCF5272_FEC_TX_BD_TO2 0x1000 +#define MCF5272_FEC_TX_BD_L 0x0800 +#define MCF5272_FEC_TX_BD_TC 0x0400 +#define MCF5272_FEC_TX_BD_DEF 0x0200 +#define MCF5272_FEC_TX_BD_HB 0x0100 +#define MCF5272_FEC_TX_BD_LC 0x0080 +#define MCF5272_FEC_TX_BD_RL 0x0040 +#define MCF5272_FEC_TX_BD_UN 0x0002 +#define MCF5272_FEC_TX_BD_CSL 0x0001 + +#define MCF5272_FEC_RX_BD_E 0x8000 +#define MCF5272_FEC_RX_BD_INUSE 0x4000 +#define MCF5272_FEC_RX_BD_R01 0x4000 +#define MCF5272_FEC_RX_BD_W 0x2000 +#define MCF5272_FEC_RX_BD_R02 0x1000 +#define MCF5272_FEC_RX_BD_L 0x0800 +#define MCF5272_FEC_RX_BD_M 0x0100 +#define MCF5272_FEC_RX_BD_BC 0x0080 +#define MCF5272_FEC_RX_BD_MC 0x0040 +#define MCF5272_FEC_RX_BD_LG 0x0020 +#define MCF5272_FEC_RX_BD_NO 0x0010 +#define MCF5272_FEC_RX_BD_SH 0x0008 +#define MCF5272_FEC_RX_BD_CR 0x0004 +#define MCF5272_FEC_RX_BD_OV 0x0002 +#define MCF5272_FEC_RX_BD_TR 0x0001 + + +/********************************************************************** +* +* USB_ Module Register Description +* +***********************************************************************/ + +/* Offsets of the registers from the MBAR */ +#define MCF5272_USB_FNR (0x1002) +#define MCF5272_USB_FNMR (0x1006) +#define MCF5272_USB_RFMR (0x100A) +#define MCF5272_USB_RFMMR (0x100E) +#define MCF5272_USB_FAR (0x1013) +#define MCF5272_USB_ASR (0x1014) +#define MCF5272_USB_DRR1 (0x1018) +#define MCF5272_USB_DRR2 (0x101C) +#define MCF5272_USB_SPECR (0x1022) +#define MCF5272_USB_EP0SR (0x1026) +#define MCF5272_USB_IEP0CFG (0x1028) +#define MCF5272_USB_OEP0CFG (0x102C) +#define MCF5272_USB_EP1CFG (0x1030) +#define MCF5272_USB_EP2CFG (0x1034) +#define MCF5272_USB_EP3CFG (0x1038) +#define MCF5272_USB_EP4CFG (0x103C) +#define MCF5272_USB_EP5CFG (0x1040) +#define MCF5272_USB_EP6CFG (0x1044) +#define MCF5272_USB_EP7CFG (0x1048) +#define MCF5272_USB_EP0CTL (0x104C) +#define MCF5272_USB_EP1CTL (0x1052) +#define MCF5272_USB_EP2CTL (0x1056) +#define MCF5272_USB_EP3CTL (0x105A) +#define MCF5272_USB_EP4CTL (0x105E) +#define MCF5272_USB_EP5CTL (0x1062) +#define MCF5272_USB_EP6CTL (0x1066) +#define MCF5272_USB_EP7CTL (0x106A) +#define MCF5272_USB_EP0ISR (0x106C) +#define MCF5272_USB_EP1ISR (0x1072) +#define MCF5272_USB_EP2ISR (0x1076) +#define MCF5272_USB_EP3ISR (0x107A) +#define MCF5272_USB_EP4ISR (0x107E) +#define MCF5272_USB_EP5ISR (0x1082) +#define MCF5272_USB_EP6ISR (0x1086) +#define MCF5272_USB_EP7ISR (0x108A) +#define MCF5272_USB_EP0IMR (0x108C) +#define MCF5272_USB_EP1IMR (0x1092) +#define MCF5272_USB_EP2IMR (0x1096) +#define MCF5272_USB_EP3IMR (0x109A) +#define MCF5272_USB_EP4IMR (0x109E) +#define MCF5272_USB_EP5IMR (0x10A2) +#define MCF5272_USB_EP6IMR (0x10A6) +#define MCF5272_USB_EP7IMR (0x10AA) +#define MCF5272_USB_EP0DR (0x10AC) +#define MCF5272_USB_EP1DR (0x10B0) +#define MCF5272_USB_EP2DR (0x10B4) +#define MCF5272_USB_EP3DR (0x10B8) +#define MCF5272_USB_EP4DR (0x10BC) +#define MCF5272_USB_EP5DR (0x10C0) +#define MCF5272_USB_EP6DR (0x10C4) +#define MCF5272_USB_EP7DR (0x10C8) +#define MCF5272_USB_EP0DPR (0x10CE) +#define MCF5272_USB_EP1DPR (0x10D2) +#define MCF5272_USB_EP2DPR (0x10D6) +#define MCF5272_USB_EP3DPR (0x10DA) +#define MCF5272_USB_EP4DPR (0x10DE) +#define MCF5272_USB_EP5DPR (0x10E2) +#define MCF5272_USB_EP6DPR (0x10E6) +#define MCF5272_USB_EP7DPR (0x10EA) +#define MCF5272_USB_CFG_RAM (0x1400) /* 0x1400 - 0x17FF */ + +/* Read access macros for general use */ +#define MCF5272_RD_USB_FNR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_FNR,16) +#define MCF5272_RD_USB_FNMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_FNMR,16) +#define MCF5272_RD_USB_RFMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_RFMR,16) +#define MCF5272_RD_USB_RFMMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_RFMMR,16) +#define MCF5272_RD_USB_FAR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_FAR,8) +#define MCF5272_RD_USB_ASR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_ASR,32) +#define MCF5272_RD_USB_DRR1(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_DRR1,32) +#define MCF5272_RD_USB_DRR2(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_DRR2,32) +#define MCF5272_RD_USB_SPECR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_SPECR,16) +#define MCF5272_RD_USB_EP0SR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0SR,16) +#define MCF5272_RD_USB_IEP0CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_IEP0CFG,32) +#define MCF5272_RD_USB_OEP0CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_OEP0CFG,32) +#define MCF5272_RD_USB_EPCFG(IMMP,EPN) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP1CFG + 4*(EPN-1),32) +#define MCF5272_RD_USB_EP1CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP1CFG,32) +#define MCF5272_RD_USB_EP2CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP2CFG,32) +#define MCF5272_RD_USB_EP3CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP3CFG,32) +#define MCF5272_RD_USB_EP4CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP4CFG,32) +#define MCF5272_RD_USB_EP5CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP5CFG,32) +#define MCF5272_RD_USB_EP6CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP6CFG,32) +#define MCF5272_RD_USB_EP7CFG(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP7CFG,32) +#define MCF5272_RD_USB_EPCTL(IMMP,EPN) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0CTL + 4*EPN,32) +#define MCF5272_RD_USB_EP0CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0CTL,32) +#define MCF5272_RD_USB_EP1CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP1CTL,16) +#define MCF5272_RD_USB_EP2CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP2CTL,16) +#define MCF5272_RD_USB_EP3CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP3CTL,16) +#define MCF5272_RD_USB_EP4CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP4CTL,16) +#define MCF5272_RD_USB_EP5CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP5CTL,16) +#define MCF5272_RD_USB_EP6CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP6CTL,16) +#define MCF5272_RD_USB_EP7CTL(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP7CTL,16) +#define MCF5272_RD_USB_EPISR(IMMP,EPN) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0ISR + 4*EPN,32) +#define MCF5272_RD_USB_EP0ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0ISR,32) +#define MCF5272_RD_USB_EP1ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP1ISR,16) +#define MCF5272_RD_USB_EP2ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP2ISR,16) +#define MCF5272_RD_USB_EP3ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP3ISR,16) +#define MCF5272_RD_USB_EP4ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP4ISR,16) +#define MCF5272_RD_USB_EP5ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP5ISR,16) +#define MCF5272_RD_USB_EP6ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP6ISR,16) +#define MCF5272_RD_USB_EP7ISR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP7ISR,16) +#define MCF5272_RD_USB_EPIMR(IMMP,EPN) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0IMR + 4*EPN,32) +#define MCF5272_RD_USB_EP0IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0IMR,32) +#define MCF5272_RD_USB_EP1IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP1IMR,16) +#define MCF5272_RD_USB_EP2IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP2IMR,16) +#define MCF5272_RD_USB_EP3IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP3IMR,16) +#define MCF5272_RD_USB_EP4IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP4IMR,16) +#define MCF5272_RD_USB_EP5IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP5IMR,16) +#define MCF5272_RD_USB_EP6IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP6IMR,16) +#define MCF5272_RD_USB_EP7IMR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP7IMR,16) +#define MCF5272_RD_USB_EPDR(IMMP,EPN,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0DR + 4*EPN,SIZE) +#define MCF5272_RD_USB_EP0DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0DR,SIZE) +#define MCF5272_RD_USB_EP1DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP1DR,SIZE) +#define MCF5272_RD_USB_EP2DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP2DR,SIZE) +#define MCF5272_RD_USB_EP3DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP3DR,SIZE) +#define MCF5272_RD_USB_EP4DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP4DR,SIZE) +#define MCF5272_RD_USB_EP5DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP5DR,SIZE) +#define MCF5272_RD_USB_EP6DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP6DR,SIZE) +#define MCF5272_RD_USB_EP7DR(IMMP,SIZE) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP7DR,SIZE) +#define MCF5272_RD_USB_EPDPR(IMMP,EPN) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0DPR + 4*EPN,16) +#define MCF5272_RD_USB_EP0DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP0DPR,16) +#define MCF5272_RD_USB_EP1DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP1DPR,16) +#define MCF5272_RD_USB_EP2DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP2DPR,16) +#define MCF5272_RD_USB_EP3DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP3DPR,16) +#define MCF5272_RD_USB_EP4DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP4DPR,16) +#define MCF5272_RD_USB_EP5DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP5DPR,16) +#define MCF5272_RD_USB_EP6DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP6DPR,16) +#define MCF5272_RD_USB_EP7DPR(IMMP) \ + Mcf5272_iord(IMMP,MCF5272_USB_EP7DPR,16) + +/* Write access macros for general use */ +#define MCF5272_WR_USB_FNR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_FNR,16,DATA) +#define MCF5272_WR_USB_FNMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_FNMR,16,DATA) +#define MCF5272_WR_USB_RFMMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_RFMMR,16,DATA) +#define MCF5272_WR_USB_EP0SR(IMMP,DATA)\ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0SR,32,DATA) +#define MCF5272_WR_USB_IEP0CFG(IMMP,DATA)\ + Mcf5272_iowr(IMMP,MCF5272_USB_IEP0CFG,32,DATA) +#define MCF5272_WR_USB_OEP0CFG(IMMP,DATA)\ + Mcf5272_iowr(IMMP,MCF5272_USB_OEP0CFG,32,DATA) +#define MCF5272_WR_USB_EPCFG(IMMP,EPN,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP1CFG + 4*(EPN-1),32,DATA) +#define MCF5272_WR_USB_EP1CFG(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP1CFG,32,DATA) +#define MCF5272_WR_USB_EP2CFG(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP2CFG,32,DATA) +#define MCF5272_WR_USB_EP3CFG(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP3CFG,32,DATA) +#define MCF5272_WR_USB_EP4CFG(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP4CFG,32,DATA) +#define MCF5272_WR_USB_EP5CFG(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP5CFG,32,DATA) +#define MCF5272_WR_USB_EP6CFG(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP6CFG,32,DATA) +#define MCF5272_WR_USB_EP7CFG(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP7CFG,32,DATA) +#define MCF5272_WR_USB_EPCTL(IMMP,EPN,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0CTL + 4*EPN,32,DATA) +#define MCF5272_WR_USB_EP0CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0CTL,32,DATA) +#define MCF5272_WR_USB_EP1CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP1CTL,16,DATA) +#define MCF5272_WR_USB_EP2CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP2CTL,16,DATA) +#define MCF5272_WR_USB_EP3CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP3CTL,16,DATA) +#define MCF5272_WR_USB_EP4CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP4CTL,16,DATA) +#define MCF5272_WR_USB_EP5CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP5CTL,16,DATA) +#define MCF5272_WR_USB_EP6CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP6CTL,16,DATA) +#define MCF5272_WR_USB_EP7CTL(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP7CTL,16,DATA) +#define MCF5272_WR_USB_EPISR(IMMP,EPN,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0ISR + 4*EPN,32,DATA) +#define MCF5272_WR_USB_EP0ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0ISR,32,DATA) +#define MCF5272_WR_USB_EP1ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP1ISR,16,DATA) +#define MCF5272_WR_USB_EP2ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP2ISR,16,DATA) +#define MCF5272_WR_USB_EP3ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP3ISR,16,DATA) +#define MCF5272_WR_USB_EP4ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP4ISR,16,DATA) +#define MCF5272_WR_USB_EP5ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP5ISR,16,DATA) +#define MCF5272_WR_USB_EP6ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP6ISR,16,DATA) +#define MCF5272_WR_USB_EP7ISR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP7ISR,16,DATA) +#define MCF5272_WR_USB_EPIMR(IMMP,EPN,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0IMR + 4*EPN,32,DATA) +#define MCF5272_WR_USB_EP0IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0IMR,32,DATA) +#define MCF5272_WR_USB_EP1IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP1IMR,16,DATA) +#define MCF5272_WR_USB_EP2IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP2IMR,16,DATA) +#define MCF5272_WR_USB_EP3IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP3IMR,16,DATA) +#define MCF5272_WR_USB_EP4IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP4IMR,16,DATA) +#define MCF5272_WR_USB_EP5IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP5IMR,16,DATA) +#define MCF5272_WR_USB_EP6IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP6IMR,16,DATA) +#define MCF5272_WR_USB_EP7IMR(IMMP,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP7IMR,16,DATA) +#define MCF5272_WR_USB_EPDR(IMMP,EPN,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0DR + 4*EPN,SIZE,DATA) +#define MCF5272_WR_USB_EP0DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP0DR,SIZE,DATA) +#define MCF5272_WR_USB_EP1DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP1DR,SIZE,DATA) +#define MCF5272_WR_USB_EP2DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP2DR,SIZE,DATA) +#define MCF5272_WR_USB_EP3DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP3DR,SIZE,DATA) +#define MCF5272_WR_USB_EP4DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP4DR,SIZE,DATA) +#define MCF5272_WR_USB_EP5DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP5DR,SIZE,DATA) +#define MCF5272_WR_USB_EP6DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP6DR,SIZE,DATA) +#define MCF5272_WR_USB_EP7DR(IMMP,SIZE,DATA) \ + Mcf5272_iowr(IMMP,MCF5272_USB_EP7DR,SIZE,DATA) + +/* Macro to return current Alternate Setting for a given Interface */ +#define AltSetting(imm, i) (int8)((MCF5272_RD_USB_ASR(imm) >> (i << 1)) & 3) + +/* Bit level definitions and macros */ +#define MCF5272_USB_EP0SR_WAKE_ST 0x0800 +#define MCF5272_USB_EP0SR_HALT_ST 0x0004 +#define MCF5272_USB_EP0SR_DIR 0x0002 + +#define MCF5272_USB_EP0CTL_DEBUG 0x00040000 +#define MCF5272_USB_EP0CTL_WOR_LVL 0x00020000 +#define MCF5272_USB_EP0CTL_WOR_EN 0x00010000 +#define MCF5272_USB_EP0CTL_CLK_SEL 0x00008000 +#define MCF5272_USB_EP0CTL_RESUME 0x00004000 +#define MCF5272_USB_EP0CTL_AFE_EN 0x00002000 +#define MCF5272_USB_EP0CTL_BUS_PWR 0x00001000 +#define MCF5272_USB_EP0CTL_USB_EN 0x00000800 +#define MCF5272_USB_EP0CTL_CFG_RAM_VAL 0x00000400 +#define MCF5272_USB_EP0CTL_CMD_ERR 0x00000200 +#define MCF5272_USB_EP0CTL_CMD_OVER 0x00000100 +#define MCF5272_USB_EP0CTL_CRC_ERR 0x00000080 +#define MCF5272_USB_EP0CTL_OUT_LVL(x) ((x & 3) << 4) +#define MCF5272_USB_EP0CTL_IN_LVL(x) ((x & 3) << 2) +#define MCF5272_USB_EP0CTL_IN_BUSY 0x00000002 + +#define MCF5272_USB_EPNCTL_CRC_ERR 0x0080 +#define MCF5272_USB_EPNCTL_ISO_MODE 0x0040 +#define MCF5272_USB_EPNCTL_FIFO_LVL(x) ((x & 3) << 2) +#define MCF5272_USB_EPNCTL_IN_BUSY 0x0002 +#define MCF5272_USB_EPNCTL_STALL 0x0001 + +#define MCF5272_USB_EP0ISR_DEV_CFG 0x00010000 +#define MCF5272_USB_EP0ISR_VEND_REQ 0x00008000 +#define MCF5272_USB_EP0ISR_FRM_MAT 0x00004000 +#define MCF5272_USB_EP0ISR_ASOF 0x00002000 +#define MCF5272_USB_EP0ISR_SOF 0x00001000 +#define MCF5272_USB_EP0ISR_WAKE_CHG 0x00000800 +#define MCF5272_USB_EP0ISR_RESUME 0x00000400 +#define MCF5272_USB_EP0ISR_SUSPEND 0x00000200 +#define MCF5272_USB_EP0ISR_RESET 0x00000100 +#define MCF5272_USB_EP0ISR_OUT_EOT 0x00000080 +#define MCF5272_USB_EP0ISR_OUT_EOP 0x00000040 +#define MCF5272_USB_EP0ISR_OUT_LVL 0x00000020 +#define MCF5272_USB_EP0ISR_IN_EOT 0x00000010 +#define MCF5272_USB_EP0ISR_IN_EOP 0x00000008 +#define MCF5272_USB_EP0ISR_UNHALT 0x00000004 +#define MCF5272_USB_EP0ISR_HALT 0x00000002 +#define MCF5272_USB_EP0ISR_IN_LVL 0x00000001 + +#define MCF5272_USB_EPNISR_HALT_ST 0x8000 +#define MCF5272_USB_EPNISR_DIR 0x4000 +#define MCF5272_USB_EPNISR_PRES 0x2000 +#define MCF5272_USB_EPNISR_EOT 0x0010 +#define MCF5272_USB_EPNISR_EOP 0x0008 +#define MCF5272_USB_EPNISR_UNHALT 0x0004 +#define MCF5272_USB_EPNISR_HALT 0x0002 +#define MCF5272_USB_EPNISR_FIFO_LVL 0x0001 + +#define MCF5272_USB_EP0IMR_DEV_CFG_EN 0x00010000 +#define MCF5272_USB_EP0IMR_VEND_REQ_EN 0x00008000 +#define MCF5272_USB_EP0IMR_FRM_MAT_EN 0x00004000 +#define MCF5272_USB_EP0IMR_ASOF_EN 0x00002000 +#define MCF5272_USB_EP0IMR_SOF_EN 0x00001000 +#define MCF5272_USB_EP0IMR_WAKE_CHG_EN 0x00000800 +#define MCF5272_USB_EP0IMR_RESUME_EN 0x00000400 +#define MCF5272_USB_EP0IMR_SUSPEND_EN 0x00000200 +#define MCF5272_USB_EP0IMR_RESET_EN 0x00000100 +#define MCF5272_USB_EP0IMR_OUT_EOT_EN 0x00000080 +#define MCF5272_USB_EP0IMR_OUT_EOP_EN 0x00000040 +#define MCF5272_USB_EP0IMR_OUT_LVL_EN 0x00000020 +#define MCF5272_USB_EP0IMR_IN_EOT_EN 0x00000010 +#define MCF5272_USB_EP0IMR_IN_EOP_EN 0x00000008 +#define MCF5272_USB_EP0IMR_UNHALT_EN 0x00000004 +#define MCF5272_USB_EP0IMR_HALT_EN 0x00000002 +#define MCF5272_USB_EP0IMR_IN_LVL_EN 0x00000001 + +#define MCF5272_USB_EPNIMR_EOT_EN 0x0010 +#define MCF5272_USB_EPNIMR_EOP_EN 0x0008 +#define MCF5272_USB_EPNIMR_UNHALT_EN 0x0004 +#define MCF5272_USB_EPNIMR_HALT_EN 0x0002 +#define MCF5272_USB_EPNIMR_FIFO_LVL_EN 0x0001 + +/***********************************************************************/ + +/* + * Define a pointer to the MCF5272 Internal Memory Map + */ + +typedef uint8 MCF5272_IMM; + +/***********************************************************************/ + +#endif /* _CPU_MCF5272_H */ diff --git a/ports/coldfire/include/arch/perf.h b/ports/coldfire/include/arch/perf.h new file mode 100644 index 0000000..334d42a --- /dev/null +++ b/ports/coldfire/include/arch/perf.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ + +#endif /* __PERF_H__ */ diff --git a/ports/coldfire/include/arch/sys_arch.h b/ports/coldfire/include/arch/sys_arch.h new file mode 100644 index 0000000..b235fe9 --- /dev/null +++ b/ports/coldfire/include/arch/sys_arch.h @@ -0,0 +1,69 @@ +/* @(#)sys_arch.h + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: David Haas + * + */ + +#ifndef _SYS_ARCH_H +#define _SYS_ARCH_H 1 + +#include +#include +#include "netif/etharp.h" + +#define SYS_MBOX_NULL NULL +#define SYS_SEM_NULL NULL + +/* sockets needs this definition. include time.h if this is a unix system */ +struct timeval { + long tv_sec; + long tv_usec; +}; + +typedef NU_SEMAPHORE * sys_sem_t; +typedef NU_QUEUE * sys_mbox_t; +typedef NU_TASK * sys_thread_t; + +/* Functions specific to Coldfire/Nucleus */ +void +sys_setvect(u32_t vector, void (*isr_function)(void), void (*dis_funct)(void)); +u32_t +sys_disable_interrupts(void); +void +sys_restore_interrupts(u32_t old_level); +void +sys_get_eth_addr(struct eth_addr *eth_addr); +int * +sys_arch_errno(void); + + +#include "arch/errno.h" + +#endif /* _SYS_ARCH_H */ + diff --git a/ports/coldfire/include/netif/5272fec.h b/ports/coldfire/include/netif/5272fec.h new file mode 100644 index 0000000..bf77928 --- /dev/null +++ b/ports/coldfire/include/netif/5272fec.h @@ -0,0 +1,44 @@ +/* @(#)5272fec.h + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Purpose: MCF5272 fec ethernet driver + * + * Author: David Haas + * + */ + +#ifndef _5272FEC_H +#define _5272FEC_H 1 + + +void +mcf5272fecif_init(struct netif *netif); + + +#endif /* _5272FEC_H */ + diff --git a/ports/coldfire/include/netif/tcpdump.h b/ports/coldfire/include/netif/tcpdump.h new file mode 100644 index 0000000..56c7834 --- /dev/null +++ b/ports/coldfire/include/netif/tcpdump.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_TCPDUMP_H__ +#define __NETIF_TCPDUMP_H__ + +#include "lwip/pbuf.h" + +void tcpdump(struct pbuf *p); + +#endif /* __NETIF_TCPDUMP_H__ */ diff --git a/ports/coldfire/netif/5272fec.c b/ports/coldfire/netif/5272fec.c new file mode 100644 index 0000000..db74fd5 --- /dev/null +++ b/ports/coldfire/netif/5272fec.c @@ -0,0 +1,787 @@ +/* + * Copyright (c) 2001-2003, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: David Haas dhaas@alum.rpi.edu + * + */ + +/* This is an ethernet driver for the internal fec in the Coldfire MCF5272. + The driver has been written to use ISRs for Receive Frame and Transmit Frame + Complete. +*/ + +#include "lwip/debug.h" + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/sys.h" + +#include "netif/etharp.h" + +#include "arch/mcf5272.h" + +/* Sizing the descriptor rings will depend upon how many pbufs you have available + * and how big they are. Also on how many frames you might want to input before dropping + * frames. Generally it is a good idea to buffer one tcp window. This means that + * you won't get a tcp retransmit and your tcp transmissions will be reasonably fast. + */ +#define NUM_RXBDS 64 // Number of receive descriptor rings +#define NUM_TXBDS 32 // Number of transmit descriptor rings + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 't' + +/* Define interface MTU size. We set this to 1518, since this is the max + Size of an ethernet frame without VLAN support. */ +#define MTU_FEC 1518 + +PACK_STRUCT_BEGIN +struct rxbd +{ + u16_t flags; + u16_t data_len; + u8_t *p_buf; +}; +PACK_STRUCT_END +typedef struct rxbd rxbd_t; + +PACK_STRUCT_BEGIN +struct txbd +{ + u16_t flags; + u16_t data_len; + u8_t *p_buf; +}; +PACK_STRUCT_END +typedef struct txbd txbd_t; + +ALIGN_STRUCT_8_BEGIN +struct mcf5272if +{ + rxbd_t rxbd_a[NUM_RXBDS]; // Rx descriptor ring. Must be aligned to double-word + txbd_t txbd_a[NUM_TXBDS]; // Tx descriptor ring. Must be aligned to double-word + struct pbuf *rx_pbuf_a[NUM_RXBDS]; // Array of pbufs corresponding to payloads in rx desc ring. + struct pbuf *tx_pbuf_a[NUM_TXBDS]; // Array of pbufs corresponding to payloads in tx desc ring. + unsigned int rx_remove; // Index that driver will remove next rx frame from. + unsigned int rx_insert; // Index that driver will insert next empty rx buffer. + unsigned int tx_insert; // Index that driver will insert next tx frame to. + unsigned int tx_remove; // Index that driver will clean up next tx buffer. + unsigned int tx_free; // Number of free transmit descriptors. + unsigned int rx_buf_len; // number of bytes in a rx buffer (that we can use). + MCF5272_IMM *imm; // imm address. All register accesses use this as base. + struct eth_addr *ethaddr; + struct netif *netif; +}; +ALIGN_STRUCT_END + +typedef struct mcf5272if mcf5272if_t; + +#define INC_RX_BD_INDEX(idx) do { if (++idx >= NUM_RXBDS) idx = 0; } while (0) +#define INC_TX_BD_INDEX(idx) do { if (++idx >= NUM_TXBDS) idx = 0; } while (0) +#define DEC_TX_BD_INDEX(idx) do { if (idx-- == 0) idx = NUM_TXBDS-1; } while (0) + +static mcf5272if_t *mcf5272if; +static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; + +u32_t phy; + +typedef struct mcf5272if mcf5272if_t; + +/*-----------------------------------------------------------------------------------*/ +static void +fill_rx_ring(mcf5272if_t *mcf5272) +{ + struct pbuf *p; + struct rxbd *p_rxbd; + int i = mcf5272->rx_insert; + void *new_payload; + u32_t u_p_pay; + + /* Try and fill as many receive buffers as we can */ + while (mcf5272->rx_pbuf_a[i] == 0) + { + p = pbuf_alloc(PBUF_RAW, (u16_t) mcf5272->rx_buf_len, PBUF_POOL); + if (p == 0) + /* No pbufs, so can't refill ring */ + return; + /* Align payload start to be divisible by 16 as required by HW */ + u_p_pay = (u32_t) p->payload; + new_payload = p->payload = (void *) (((u_p_pay + 15) / 16) * 16); + + mcf5272->rx_pbuf_a[i] = p; + p_rxbd = &mcf5272->rxbd_a[i]; + p_rxbd->p_buf = (u8_t *) new_payload; + p_rxbd->flags = (p_rxbd->flags & MCF5272_FEC_RX_BD_W) | MCF5272_FEC_RX_BD_E; + INC_RX_BD_INDEX(mcf5272->rx_insert); + i = mcf5272->rx_insert; + } +} + +/*-----------------------------------------------------------------------------------*/ +static void +enable_fec(mcf5272if_t *mcf5272) +{ + MCF5272_IMM *imm = mcf5272->imm; + int i; + + /* Initialize empty tx descriptor ring */ + for(i = 0; i < NUM_TXBDS-1; i++) + mcf5272->txbd_a[i].flags = 0; + /* Set wrap bit for last descriptor */ + mcf5272->txbd_a[i].flags = MCF5272_FEC_TX_BD_W; + /* initialize tx indexes */ + mcf5272->tx_remove = mcf5272->tx_insert = 0; + mcf5272->tx_free = NUM_TXBDS; + + /* Initialize empty rx descriptor ring */ + for (i = 0; i < NUM_RXBDS-1; i++) + mcf5272->rxbd_a[i].flags = 0; + /* Set wrap bit for last descriptor */ + mcf5272->rxbd_a[i].flags = MCF5272_FEC_RX_BD_W; + /* Initialize rx indexes */ + mcf5272->rx_remove = mcf5272->rx_insert = 0; + + /* Fill receive descriptor ring */ + fill_rx_ring(mcf5272); + + /* Enable FEC */ + MCF5272_WR_FEC_ECR(imm, (MCF5272_FEC_ECR_ETHER_EN));// | 0x2000000)); + + /* Indicate that there have been empty receive buffers produced */ + MCF5272_WR_FEC_RDAR(imm,1); +} + + +/*-----------------------------------------------------------------------------------*/ +static void +disable_fec(mcf5272if_t *mcf5272) +{ + MCF5272_IMM *imm = mcf5272->imm; + int i; + u32_t value; + u32_t old_level; + + /* We need to disable interrupts here, It is important when dealing with shared + registers. */ + old_level = sys_disable_interrupts(); + + /* First disable the FEC interrupts. Do it in the appropriate ICR register. */ + value = MCF5272_RD_SIM_ICR3(imm); + MCF5272_WR_SIM_ICR3(imm, (value & ~(MCF5272_SIM_ICR_ERX_IL(7) | + MCF5272_SIM_ICR_ETX_IL(7) | + MCF5272_SIM_ICR_ENTC_IL(7)))); + + /* Now we can restore interrupts. This is because we can assume that + * we are single threaded here (only 1 thread will be calling disable_fec + * for THIS interface). */ + sys_restore_interrupts(old_level); + + /* Release all buffers attached to the descriptors. Since the driver + * ALWAYS zeros the pbuf array locations and descriptors when buffers are + * removed, we know we just have to free any non-zero descriptors */ + for (i = 0; i < NUM_RXBDS; i++) + if (mcf5272->rx_pbuf_a[i]) + { + pbuf_free(mcf5272->rx_pbuf_a[i]); + mcf5272->rx_pbuf_a[i] = 0; + mcf5272->rxbd_a->p_buf = 0; + } + for (i = 0; i < NUM_TXBDS; i++) + if (mcf5272->tx_pbuf_a[i]) + { + pbuf_free(mcf5272->tx_pbuf_a[i]); + mcf5272->tx_pbuf_a[i] = 0; + mcf5272->txbd_a->p_buf = 0; + } + + /* Reset the FEC - equivalent to a hard reset */ + MCF5272_WR_FEC_ECR(imm,MCF5272_FEC_ECR_RESET); + /* Wait for the reset sequence to complete, it should take about 16 clock cycles */ + i = 0; + while (MCF5272_RD_FEC_ECR(imm) & MCF5272_FEC_ECR_RESET) + { + if (++i > 100) + abort(); + } + + /* Disable all FEC interrupts by clearing the IMR register */ + MCF5272_WR_FEC_IMR(imm,0); + /* Clear any interrupts by setting all bits in the EIR register */ + MCF5272_WR_FEC_EIR(imm,0xFFFFFFFF); +} + +/*-----------------------------------------------------------------------------------* + * Function called by receive LISR to disable fec tx interrupt + *-----------------------------------------------------------------------------------*/ +static void +mcf5272_dis_tx_int(void) +{ + mcf5272if_t *mcf5272 = mcf5272if; + MCF5272_IMM *imm = mcf5272->imm; + u32_t value; + + value = MCF5272_RD_FEC_IMR(imm); + /* Clear rx interrupt bit */ + MCF5272_WR_FEC_IMR(imm, (value & ~MCF5272_FEC_IMR_TXFEN)); + return; +} + +/*-----------------------------------------------------------------------------------* + *-----------------------------------------------------------------------------------*/ +static void +mcf5272fec_tx_cleanup(void) +{ + struct pbuf *p; + mcf5272if_t *mcf5272 = mcf5272if; + MCF5272_IMM *imm = mcf5272->imm; + u32_t value; + u32_t old_level; + unsigned int tx_remove_sof; + unsigned int tx_remove_eof; + unsigned int i; + u16_t flags; + + + tx_remove_sof = tx_remove_eof = mcf5272->tx_remove; + + /* Loop, looking for completed buffers at eof */ + while ((((flags = mcf5272->txbd_a[tx_remove_eof].flags) & MCF5272_FEC_TX_BD_R) == 0) && + (mcf5272->tx_pbuf_a[tx_remove_eof] != 0)) + { + /* See if this is last buffer in frame */ + if ((flags & MCF5272_FEC_TX_BD_L) != 0) + { + i = tx_remove_eof; + /* This frame is complete. Take the frame off backwards */ + do + { + p = mcf5272->tx_pbuf_a[i]; + mcf5272->tx_pbuf_a[i] = 0; + mcf5272->txbd_a[i].p_buf = 0; + mcf5272->tx_free++; + if (i != tx_remove_sof) + DEC_TX_BD_INDEX(i); + else + break; + } while (1); + + pbuf_free(p); // Will be head of chain + /* Look at next descriptor */ + INC_TX_BD_INDEX(tx_remove_eof); + tx_remove_sof = tx_remove_eof; + } + else + INC_TX_BD_INDEX(tx_remove_eof); + } + mcf5272->tx_remove = tx_remove_eof; + + /* clear interrupt status for tx interrupt */ + old_level = sys_disable_interrupts(); + MCF5272_WR_FEC_EIR(imm, MCF5272_FEC_EIR_TXF); + value = MCF5272_RD_FEC_IMR(imm); + /* Set tx interrupt bit again */ + MCF5272_WR_FEC_IMR(imm, (value | MCF5272_FEC_IMR_TXFEN)); + /* Now we can re-enable higher priority interrupts again */ + sys_restore_interrupts(old_level); +} + + +/*-----------------------------------------------------------------------------------* + void low_level_output(mcf5272if_t *mcf5272, struct pbuf *p) + + Output pbuf chain to hardware. It is assumed that there is a complete and correct + ethernet frame in p. The only buffering we have in this system is in the + hardware descriptor ring. If there is no room on the ring, then drop the frame. + *-----------------------------------------------------------------------------------*/ +static err_t +low_level_output(struct netif *netif, struct pbuf *p) +{ + struct pbuf *q; + mcf5272if_t *mcf5272 = netif->state; + MCF5272_IMM *imm = mcf5272->imm; + int num_desc; + int num_free; + unsigned int tx_insert_sof, tx_insert_eof; + unsigned int i; + u32_t old_level; + + /* Interrupts are disabled through this whole thing to support multi-threading + * transmit calls. Also this function might be called from an ISR. */ + old_level = sys_disable_interrupts(); + + /* Determine number of descriptors needed */ + num_desc = pbuf_clen(p); + if (num_desc > mcf5272->tx_free) + { + /* Drop the frame, we have no place to put it */ + pbuf_free(p); +#ifdef LINK_STATS + lwip_stats.link.memerr++; +#endif + sys_restore_interrupts(old_level); + return ERR_MEM; + + } else { + /* Increment use count on pbuf */ + pbuf_ref(p); + + /* Put buffers on descriptor ring, but don't mark them as ready yet */ + tx_insert_eof = tx_insert_sof = mcf5272->tx_insert; + q = p; + do + { + mcf5272->tx_free--; + mcf5272->tx_pbuf_a[tx_insert_eof] = q; + mcf5272->txbd_a[tx_insert_eof].p_buf = q->payload; + mcf5272->txbd_a[tx_insert_eof].data_len = q->len; + q = q->next; + if (q) + INC_TX_BD_INDEX(tx_insert_eof); + } while (q); + + /* Go backwards through descriptor ring setting flags */ + i = tx_insert_eof; + do + { + mcf5272->txbd_a[i].flags = (u16_t) (MCF5272_FEC_TX_BD_R | + (mcf5272->txbd_a[i].flags & MCF5272_FEC_TX_BD_W) | + ((i == tx_insert_eof) ? (MCF5272_FEC_TX_BD_L | MCF5272_FEC_TX_BD_TC) : 0)); + if (i != tx_insert_sof) + DEC_TX_BD_INDEX(i); + else + break; + } while (1); + INC_TX_BD_INDEX(tx_insert_eof); + mcf5272->tx_insert = tx_insert_eof; +#ifdef LINK_STATS + lwip_stats.link.xmit++; +#endif + /* Indicate that there has been a transmit buffer produced */ + MCF5272_WR_FEC_TDAR(imm,1); + sys_restore_interrupts(old_level); + } + return ERR_OK; +} + +/*-----------------------------------------------------------------------------------*/ +/* + * This function is called by the TCP/IP stack when an IP packet + * should be sent. It calls the function called low_level_output() to + * do the actuall transmission of the packet. + * + */ +/*-----------------------------------------------------------------------------------*/ +static err_t +mcf5272fecif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr) +{ + p = etharp_output(netif, ipaddr, p); + if(p != NULL) { + low_level_output(netif, p); + } + return ERR_OK; + +} + +/*-----------------------------------------------------------------------------------*/ +static void +eth_input(struct pbuf *p, struct netif *netif) +{ + /* Ethernet protocol layer */ + struct eth_hdr *ethhdr; + mcf5272if_t *mcf5272 = netif->state; + struct pbuf *q = NULL; + + ethhdr = p->payload; + + switch(htons(ethhdr->type)) { + case ETHTYPE_IP: + q = etharp_ip_input(netif, p); + pbuf_header(p, -14); + netif->input(p, netif); + break; + case ETHTYPE_ARP: + q = etharp_arp_input(netif, mcf5272->ethaddr, p); + break; + default: + pbuf_free(p); + break; + } + if(q != NULL) { + low_level_output(netif, q); + pbuf_free(q); + } +} + +/*-----------------------------------------------------------------------------------*/ +static void +arp_timer(void *arg) +{ + etharp_tmr(); + sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler)arp_timer, NULL); +} + +/*-----------------------------------------------------------------------------------* + * Function called by receive LISR to disable fec rx interrupt + *-----------------------------------------------------------------------------------*/ +static void +mcf5272_dis_rx_int(void) +{ + mcf5272if_t *mcf5272 = mcf5272if; + MCF5272_IMM *imm = mcf5272->imm; + u32_t value; + + value = MCF5272_RD_FEC_IMR(imm); + /* Clear rx interrupt bit */ + MCF5272_WR_FEC_IMR(imm, (value & ~MCF5272_FEC_IMR_RXFEN)); + return; +} + +/*-----------------------------------------------------------------------------------*/ +static void +mcf5272fec_rx(void) +{ + /* This is the receive ISR. It is written to be a high-level ISR. */ + u32_t old_level; + mcf5272if_t *mcf5272 = mcf5272if; + MCF5272_IMM *imm = mcf5272->imm; + u32_t value; + u16_t flags; + unsigned int rx_remove_sof; + unsigned int rx_remove_eof; + struct pbuf *p; + + + rx_remove_sof = rx_remove_eof = mcf5272->rx_remove; + + /* Loop, looking for filled buffers at eof */ + while ((((flags = mcf5272->rxbd_a[rx_remove_eof].flags) & MCF5272_FEC_RX_BD_E) == 0) && + (mcf5272->rx_pbuf_a[rx_remove_eof] != 0)) + { + /* See if this is last buffer in frame */ + if ((flags & MCF5272_FEC_RX_BD_L) != 0) + { + /* This frame is ready to go. Start at first descriptor in frame. */ + p = 0; + do + { + /* Adjust pbuf length if this is last buffer in frame */ + if (rx_remove_sof == rx_remove_eof) + { + mcf5272->rx_pbuf_a[rx_remove_sof]->tot_len = + mcf5272->rx_pbuf_a[rx_remove_sof]->len = (u16_t) + (mcf5272->rxbd_a[rx_remove_sof].data_len - (p ? p->tot_len : 0)); + } + else + mcf5272->rx_pbuf_a[rx_remove_sof]->len = + mcf5272->rx_pbuf_a[rx_remove_sof]->tot_len = mcf5272->rxbd_a[rx_remove_sof].data_len; + + /* Chain pbuf */ + if (p == 0) + { + p = mcf5272->rx_pbuf_a[rx_remove_sof]; // First in chain + p->tot_len = p->len; // Important since len might have changed + } + else + pbuf_chain(p, mcf5272->rx_pbuf_a[rx_remove_sof]); + /* Clear pointer to mark descriptor as free */ + mcf5272->rx_pbuf_a[rx_remove_sof] = 0; + mcf5272->rxbd_a[rx_remove_sof].p_buf = 0; + + if (rx_remove_sof != rx_remove_eof) + INC_RX_BD_INDEX(rx_remove_sof); + else + break; + + } while (1); + INC_RX_BD_INDEX(rx_remove_sof); + + /* Check error status of frame */ + if (flags & (MCF5272_FEC_RX_BD_LG | + MCF5272_FEC_RX_BD_NO | + MCF5272_FEC_RX_BD_CR | + MCF5272_FEC_RX_BD_OV)) + { +#ifdef LINK_STATS + lwip_stats.link.drop++; + if (flags & MCF5272_FEC_RX_BD_LG) + lwip_stats.link.lenerr++; //Jumbo gram + else + if (flags & (MCF5272_FEC_RX_BD_NO | MCF5272_FEC_RX_BD_OV)) + lwip_stats.link.err++; + else + if (flags & MCF5272_FEC_RX_BD_CR) + lwip_stats.link.chkerr++; // CRC errors +#endif + /* Drop errored frame */ + pbuf_free(p); + } else { + /* Good frame. increment stat */ +#ifdef LINK_STATS + lwip_stats.link.recv++; +#endif + eth_input(p, mcf5272->netif); + } + } + INC_RX_BD_INDEX(rx_remove_eof); + } + mcf5272->rx_remove = rx_remove_sof; + + /* clear interrupt status for rx interrupt */ + old_level = sys_disable_interrupts(); + MCF5272_WR_FEC_EIR(imm, MCF5272_FEC_EIR_RXF); + value = MCF5272_RD_FEC_IMR(imm); + /* Set rx interrupt bit again */ + MCF5272_WR_FEC_IMR(imm, (value | MCF5272_FEC_IMR_RXFEN)); + /* Now we can re-enable higher priority interrupts again */ + sys_restore_interrupts(old_level); + + /* Fill up empty descriptor rings */ + fill_rx_ring(mcf5272); + /* Tell fec that we have filled up her ring */ + MCF5272_WR_FEC_RDAR(imm, 1); + + return; +} + + + +/*-----------------------------------------------------------------------------------*/ +static void +low_level_init(struct netif *netif) +{ + mcf5272if_t *mcf5272; + MCF5272_IMM *imm; + VOID (*old_lisr)(INT); /* old LISR */ + u32_t value; + u32_t old_level; + struct pbuf *p; + int i; + + mcf5272 = netif->state; + imm = mcf5272->imm; + + /* Initialize our ethernet address */ + sys_get_eth_addr(mcf5272->ethaddr); + + /* First disable fec */ + disable_fec(mcf5272); + + /* Plug appropriate low level interrupt vectors */ + sys_setvect(MCF5272_VECTOR_ERx, mcf5272fec_rx, mcf5272_dis_rx_int); + sys_setvect(MCF5272_VECTOR_ETx, mcf5272fec_tx_cleanup, mcf5272_dis_tx_int); + //sys_setvect(MCF5272_VECTOR_ENTC, mcf5272fec_ntc); + + /* Set the I_MASK register to enable only rx & tx frame interrupts */ + MCF5272_WR_FEC_IMR(imm, MCF5272_FEC_IMR_TXFEN | MCF5272_FEC_IMR_RXFEN); + + /* Clear I_EVENT register */ + MCF5272_WR_FEC_EIR(imm,0xFFFFFFFF); + + /* Set up the appropriate interrupt levels */ + /* Disable interrupts, since this is a read/modify/write operation */ + old_level = sys_disable_interrupts(); + value = MCF5272_RD_SIM_ICR3(imm); + MCF5272_WR_SIM_ICR3(imm, value | MCF5272_SIM_ICR_ERX_IL(FEC_LEVEL) | + MCF5272_SIM_ICR_ETX_IL(FEC_LEVEL)); + sys_restore_interrupts(old_level); + + /* Set the source address for the controller */ + MCF5272_WR_FEC_MALR(imm,0 + | (mcf5272->ethaddr->addr[0] <<24) + | (mcf5272->ethaddr->addr[1] <<16) + | (mcf5272->ethaddr->addr[2] <<8) + | (mcf5272->ethaddr->addr[3] <<0)); + MCF5272_WR_FEC_MAUR(imm,0 + | (mcf5272->ethaddr->addr[4] <<24) + | (mcf5272->ethaddr->addr[5] <<16)); + + /* Initialize the hash table registers */ + /* We are not supporting multicast addresses */ + MCF5272_WR_FEC_HTUR(imm,0); + MCF5272_WR_FEC_HTLR(imm,0); + + /* Set Receive Buffer Size. We subtract 16 because the start of the receive + * buffer MUST be divisible by 16, so depending on where the payload really + * starts in the pbuf, we might be increasing the start point by up to 15 bytes. + * See the alignment code in fill_rx_ring() */ + /* There might be an offset to the payload address and we should subtract + * that offset */ + p = pbuf_alloc(PBUF_RAW, PBUF_POOL_BUFSIZE, PBUF_POOL); + i = 0; + if (p) + { + struct pbuf *q = p; + + while ((q = q->next) != 0) + i += q->len; + mcf5272->rx_buf_len = PBUF_POOL_BUFSIZE-16-i; + pbuf_free(p); + } + + + MCF5272_WR_FEC_EMRBR(imm, (u16_t) mcf5272->rx_buf_len); + + /* Point to the start of the circular Rx buffer descriptor queue */ + MCF5272_WR_FEC_ERDSR(imm, ((u32_t) &mcf5272->rxbd_a[0])); + + /* Point to the start of the circular Tx buffer descriptor queue */ + MCF5272_WR_FEC_ETDSR(imm, ((u32_t) &mcf5272->txbd_a[0])); + + /* Set the tranceiver interface to MII mode */ + MCF5272_WR_FEC_RCR(imm, 0 + | MCF5272_FEC_RCR_MII_MODE); + /* | MCF5272_FEC_RCR_DRT); */ /* half duplex */ + + /* Only operate in half-duplex, no heart beat control */ + MCF5272_WR_FEC_TCR(imm, 0); + + /* Set the maximum frame length (MTU) */ + MCF5272_WR_FEC_MFLR(imm, MTU_FEC); + + /* Set MII bus speed */ + MCF5272_WR_FEC_MSCR(imm, 0x0a); + + /* Enable fec i/o pins */ + value = MCF5272_RD_GPIO_PBCNT(imm); + MCF5272_WR_GPIO_PBCNT(imm, ((value & 0x0000ffff) | 0x55550000)); + + /* Clear MII interrupt status */ + MCF5272_WR_FEC_EIR(imm, MCF5272_FEC_IMR_MIIEN); + +/* /\* Read phy ID *\/ */ +/* MCF5272_WR_FEC_MMFR(imm, 0x600a0000); */ +/* while (1) */ +/* { */ +/* value = MCF5272_RD_FEC_EIR(imm); */ +/* if ((value & MCF5272_FEC_IMR_MIIEN) != 0) */ +/* { */ +/* MCF5272_WR_FEC_EIR(imm, MCF5272_FEC_IMR_MIIEN); */ +/* break; */ +/* } */ +/* } */ +/* phy = MCF5272_RD_FEC_MMFR(imm); */ + + /* Enable FEC */ + enable_fec(mcf5272); + + /* THIS IS FOR LEVEL ONE/INTEL PHY ONLY!!! */ + /* Program Phy LED 3 to tell us transmit status */ + MCF5272_WR_FEC_MMFR(imm, 0x50520412); + +} + +/*-----------------------------------------------------------------------------------* + * etharp timer thread + * It's only job is to initialize the timer, create a semaphore and wait on it + * forever. We need a special task to handle the arp timer. + *-----------------------------------------------------------------------------------*/ +static void +etharp_timer_thread(void *arg) +{ + sys_sem_t *psem = (sys_sem_t *) arg; + sys_sem_t sem; + + /* Create timeout timer */ + sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler)arp_timer, NULL); + /* Signal previous task that it can go */ + sys_sem_signal(*psem); + + sem = sys_sem_new(0); + + while(1) + { + sys_sem_wait(sem); + } +} + + + +/*-----------------------------------------------------------------------------------*/ +static void +etharp_timer_init(void *arg) +{ + sys_thread_new((void *)etharp_timer_thread, arg); +} + + +/*-----------------------------------------------------------------------------------*/ +/* + * mcf5272fecif_init(struct netif *netif): + * + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + * Note that there is only one fec in a 5272! + * + */ +void +mcf5272fecif_init(struct netif *netif) +{ + sys_sem_t sem; + + /* Allocate our interface control block */ + /* IMPORTANT NOTE: This works for 5272, but if you are using a cpu with data cache + * then you need to make sure you get this memory from non-cachable memory. */ + mcf5272if = (mcf5272if_t *) calloc(1, sizeof(mcf5272if_t)); + if (mcf5272if) + { + netif->state = mcf5272if; + mcf5272if->netif = netif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + netif->output = mcf5272fecif_output; + netif->linkoutput = low_level_output; + netif->mtu = MTU_FEC - 18; // mtu without ethernet header and crc + mcf5272if->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); + mcf5272if->imm = mcf5272_get_immp(); + + low_level_init(netif); + + etharp_init(); + sem = sys_sem_new(0); + etharp_timer_init(&sem); + sys_sem_wait(sem); + sys_sem_free(sem); + + + } + /* + else + Give some error message if we are out of memory + */ +} + +/*-----------------------------------------------------------------------------------*/ diff --git a/ports/coldfire/netif/tcpdump.c b/ports/coldfire/netif/tcpdump.c new file mode 100644 index 0000000..6957fcd --- /dev/null +++ b/ports/coldfire/netif/tcpdump.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "netif/tcpdump.h" +#include "lwip/ip.h" +#include "lwip/tcp.h" +#include "lwip/udp.h" +#include "lwip/inet.h" + +/*-----------------------------------------------------------------------------------*/ +void +tcpdump(struct pbuf *p) +{ +} +/*-----------------------------------------------------------------------------------*/ + + + + diff --git a/ports/coldfire/perf.c b/ports/coldfire/perf.c new file mode 100644 index 0000000..689a587 --- /dev/null +++ b/ports/coldfire/perf.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "arch/perf.h" + +void +perf_init(char *fname) +{ +} diff --git a/ports/coldfire/sys_arch.c b/ports/coldfire/sys_arch.c new file mode 100644 index 0000000..e78980d --- /dev/null +++ b/ports/coldfire/sys_arch.c @@ -0,0 +1,574 @@ +/* @(#)sys_arch.c + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: David Haas + * + */ + +#include "lwip/debug.h" + +#include "lwip/sys.h" +#include "lwip/opt.h" +#include "lwip/stats.h" + +#include "nucleus.h" +#include "config.h" +#include +#include + +struct sys_thread { + struct sys_thread *next; + struct sys_timeouts timeouts; + int errno_i; + NU_TASK *pthread; + void (*function)(void *arg); + void *arg; +}; + +struct sys_hisr +{ + struct sys_hisr *next; + NU_HISR *hisr; + void (*disablefun) (void); + u32_t vector; +}; + +static int num_sem = 0; // Number of semaphores created +static int num_mbox = 0; // Number of mailboxes created +static int num_thread = 0; // Number of threads created +static int num_hisr = 0; // Number of hisrs created +static sys_sem_t thread_sem; // Protect thread structure +static struct sys_thread *threads = NULL; +static struct sys_hisr *hisrs = NULL; + +#define TICKS_PER_SECOND 10000 +#define MS_TO_TICKS(MS) (MS * TICKS_PER_SECOND) / 1000 +#define TICKS_TO_MS(TICKS) (1000 * TICKS) / TICKS_PER_SECOND + +#define SYS_MBOX_SIZE 128 // Number of elements in mbox queue +#define SYS_STACK_SIZE 2048 // A minimum Nucleus stack for coldfire +#define SYS_HISR_STACK_SIZE 2048 // A minimum Nucleus stack for coldfire +/* People often make a mistake on the priority of their communications task. + The TCP/IP stack should be at a relatively low priority if it is an endpoint + (not a router) on a somewhat underpowered CPU. You are'nt going to keep up + with network traffic during a denial of service attack or misconfigured network + and you don't want an overburdened network task to cause other important tasks + (including your UI) to stop working. Drop packets! It forces flow control and + lets the rest of your system run. +*/ +#define SYS_THREAD_PRIORITY 220 // Relatively low priority + +/*---------------------------------------------------------------------------------*/ +void +sys_init(void) +{ + thread_sem = sys_sem_new(1); + return; +} + +/*---------------------------------------------------------------------------------*/ +static void +sys_thread_entry(UNSIGNED argc, VOID *argv) +{ + /* argv is passed as a pointer to our thread structure */ + struct sys_thread *p_thread = (struct sys_thread *)argv; + + p_thread->function(p_thread->arg); +} + +/*---------------------------------------------------------------------------------*/ +static struct sys_thread * +introduce_thread(NU_TASK *id, void (*function)(void *arg), void *arg) +{ + struct sys_thread *thread; + + thread = (struct sys_thread *) calloc(1,sizeof(struct sys_thread)); + + if(thread) { + sys_arch_sem_wait(thread_sem, 0); //Wait to obtain the semaphore + thread->next = threads; + thread->timeouts.next = NULL; + thread->pthread = id; + thread->function = function; + thread->arg = arg; + threads = thread; + sys_sem_signal(thread_sem); //Release semaphore + } + + return thread; +} + +/*---------------------------------------------------------------------------------*/ +/* We use Nucleus task as thread. Create one with a standard size stack at a standard + * priority. */ +void +sys_thread_new(void (*function)(void *arg), void *arg) +{ + NU_TASK *p_thread; + u8_t *p_stack; + STATUS status; + char thread_name[8] = " "; + struct sys_thread *st; + + p_stack = (u8_t *) malloc(SYS_STACK_SIZE); + if (p_stack) + { + p_thread = (NU_TASK *) calloc(1,sizeof(NU_TASK)); + if (p_thread) + { + /* get a new thread structure */ + st = introduce_thread(p_thread, function, arg); + if (st) + { + num_thread = (num_thread +1) % 100; // Only count to 99 + sprintf(thread_name, "lwip%02d", num_thread); + thread_name[strlen(thread_name)] = ' '; + + status = NU_Create_Task(p_thread, + thread_name, + sys_thread_entry, + 0, + st, + p_stack, + SYS_STACK_SIZE, + SYS_THREAD_PRIORITY, + 0, //Disable timeslicing + NU_PREEMPT, + NU_START); + if (status == NU_SUCCESS) + return; + } + + } + } + abort(); +} + +/*-----------------------------------------------------------------------------------*/ +static struct sys_thread * +current_thread(void) +{ + struct sys_thread *st; + NU_TASK *pt; + + pt = NU_Current_Task_Pointer(); + sys_arch_sem_wait(thread_sem, 0); + + for(st = threads; st != NULL; st = st->next) + { + if(st->pthread == pt) + { + sys_sem_signal(thread_sem); + + return st; + } + } + + sys_sem_signal(thread_sem); + + st = introduce_thread(pt, 0, 0); + + if(!st) { + abort(); + } + + return st; +} + + +/*---------------------------------------------------------------------------------*/ +struct sys_timeouts * +sys_arch_timeouts(void) +{ + struct sys_thread *thread; + + thread = current_thread(); + return &thread->timeouts; +} +/*---------------------------------------------------------------------------------*/ +int * +sys_arch_errno(void) +{ + struct sys_thread *thread; + + thread = current_thread(); + return &thread->errno_i; +} + +/*---------------------------------------------------------------------------------*/ +sys_sem_t +sys_sem_new(u8_t count) +{ + STATUS status; + NU_SEMAPHORE *sem; + char sem_name[8] = " "; + +#ifdef SYS_STATS + lwip_stats.sys.sem.used++; + if(lwip_stats.sys.sem.used > lwip_stats.sys.sem.max) + { + lwip_stats.sys.sem.max = lwip_stats.sys.sem.used; + } +#endif /* SYS_STATS */ + + /* Get memory for new semaphore */ + sem = (NU_SEMAPHORE *) calloc(1,sizeof(NU_SEMAPHORE)); + + if (sem) + { + /* Create a unique name for semaphore based on number created */ + num_sem = (num_sem + 1) % 100; // Only count to 99 + sprintf(sem_name, "lwip%02d", num_sem); + sem_name[strlen(sem_name)] = ' '; + + /* Ask nucleus to create semaphore */ + NU_Create_Semaphore(sem, + sem_name, + count, + NU_FIFO); + } + return sem; +} + +/*---------------------------------------------------------------------------------*/ +void +sys_sem_free(sys_sem_t sem) +{ + if (sem != SYS_SEM_NULL) + { +#ifdef SYS_STATS + lwip_stats.sys.sem.used--; +#endif /* SYS_STATS */ + NU_Delete_Semaphore(sem); + free(sem); + } +} + +/*---------------------------------------------------------------------------------*/ +void +sys_sem_signal(sys_sem_t sem) +{ + NU_Release_Semaphore(sem); +} + +/*---------------------------------------------------------------------------------*/ +u16_t +sys_arch_sem_wait(sys_sem_t sem, u16_t timeout) +{ + UNSIGNED timestart, timespent; + STATUS status; + + /* Get the current time */ + timestart = NU_Retrieve_Clock(); + /* Wait for the semaphore */ + status = NU_Obtain_Semaphore(sem, + timeout ? MS_TO_TICKS(timeout) : NU_SUSPEND); + /* This next statement takes wraparound into account. It works. Really! */ + timespent = TICKS_TO_MS(((s32_t) ((s32_t) NU_Retrieve_Clock() - (s32_t) timestart))); + + if (status == NU_TIMEOUT) + return 0; + else + return timespent ? (u16_t) timespent : 1; +} + +/*---------------------------------------------------------------------------------*/ +sys_mbox_t +sys_mbox_new(void) +{ + u32_t *p_queue_mem; + NU_QUEUE *p_queue; + char queue_name[8] = " "; + + /* Allocate memory for queue */ + p_queue_mem = (u32_t *) calloc(1,(SYS_MBOX_SIZE * sizeof(u32_t))); + if (p_queue_mem) + { + /* Allocate memory for queue control block */ + p_queue = (NU_QUEUE *) calloc(1,sizeof(NU_QUEUE)); + if (p_queue) + { + /* Create a unique name for mbox based on number created */ + num_mbox = (num_mbox + 1) % 100; + sprintf(queue_name, "lwip%02d", num_mbox); + queue_name[strlen(queue_name)] = ' '; + + NU_Create_Queue(p_queue, + queue_name, + p_queue_mem, + SYS_MBOX_SIZE, + NU_FIXED_SIZE, + 1, + NU_FIFO); +#ifdef SYS_STATS + lwip_stats.sys.mbox.used++; + if(lwip_stats.sys.mbox.used > lwip_stats.sys.mbox.max) { + lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used; + } +#endif /* SYS_STATS */ + return p_queue; + } + else + free(p_queue_mem); + } + return SYS_MBOX_NULL; +} + +/*---------------------------------------------------------------------------------*/ +void +sys_mbox_free(sys_mbox_t mbox) +{ + VOID *p_queue_mem; + CHAR name[8]; + UNSIGNED queue_size; + UNSIGNED available; + UNSIGNED messages; + OPTION message_type; + UNSIGNED message_size; + OPTION suspend_type; + UNSIGNED tasks_waiting; + NU_TASK *first_task; + STATUS status; + + if (mbox != SYS_MBOX_NULL) + { + /* First we need to get address of queue memory. Ask Nucleus + for information about the queue */ + status = NU_Queue_Information(mbox, + name, + &p_queue_mem, + &queue_size, + &available, + &messages, + &message_type, + &message_size, + &suspend_type, + &tasks_waiting, + &first_task); + if (status == NU_SUCCESS) + free(p_queue_mem); + NU_Delete_Queue(mbox); + free(mbox); +#ifdef SYS_STATS + lwip_stats.sys.mbox.used--; +#endif /* SYS_STATS */ + } + +} + +/*--------------------------------------------------------------------------------- + This function sends a message to a mailbox. It is unusual in that no error + return is made. This is because the caller is responsible for ensuring that + the mailbox queue will not fail. The caller does this by limiting the number + of msg structures which exist for a given mailbox. + ---------------------------------------------------------------------------------*/ +void +sys_mbox_post(sys_mbox_t mbox, void *msg) +{ + UNSIGNED status; + + DEBUGF(SYS_DEBUG, ("sys_mbox_post: mbox %p msg %p\n", mbox, msg)); + status = NU_Send_To_Queue(mbox, + &msg, + 1, + NU_NO_SUSPEND); + ASSERT("sys_mbox_post: mbx post failed", status == NU_SUCCESS); +} +/*---------------------------------------------------------------------------------*/ +u16_t +sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u16_t timeout) +{ + UNSIGNED timestart, timespent; + STATUS status; + void *ret_msg; + UNSIGNED actual_size; + + /* Get the current time */ + timestart = NU_Retrieve_Clock(); + + /* Wait for message */ + status = NU_Receive_From_Queue(mbox, + &ret_msg, + 1, + &actual_size, + timeout ? MS_TO_TICKS(timeout) : NU_SUSPEND); + + if (status == NU_SUCCESS) + { + if (msg) + *msg = ret_msg; + DEBUGF(SYS_DEBUG, ("sys_mbox_fetch: mbox %p msg %p\n", mbox, ret_msg)); + } + + /* This next statement takes wraparound into account. It works. Really! */ + timespent = TICKS_TO_MS(((s32_t) ((s32_t) NU_Retrieve_Clock() - (s32_t) timestart))); + + if (status == NU_TIMEOUT) + return 0; + else + return timespent ? (u16_t) timespent : 1; +} + +/*---------------------------------------------------------------------------------*/ +static void +sys_arch_lisr(INT vector_number) +{ + struct sys_hisr *p_hisr = hisrs; + + /* Determine which HISR to activate */ + while (p_hisr != NULL) + { + if (vector_number == p_hisr->vector) + { + if (p_hisr->disablefun) + (*p_hisr->disablefun)(); + NU_Activate_HISR(p_hisr->hisr); + break; + } + p_hisr = p_hisr->next; + } + return; +} + + +/*---------------------------------------------------------------------------------*/ +void +sys_setvect(u32_t vector, void (*isr_function)(void), void (*dis_funct)(void)) +{ + /* The passed function is called as a high level ISR on the selected vector. + It is assumed that all the functions in this module can be called by the + isr_function. + */ + struct sys_hisr *p_hisr = hisrs; + INT old_level; + NU_HISR *nucleus_hisr; + u8_t *p_stack; + STATUS status; + char hisr_name[8] = " "; + void (*old_lisr)(INT); + + /* In this case a Nucleus HISR is created for the isr_function. This + * requires it's own stack. Also get memory for Nucleus HISR. */ + nucleus_hisr = (NU_HISR *) calloc(1,sizeof(NU_HISR)); + if (nucleus_hisr) + { + p_stack = (u8_t *) malloc(SYS_HISR_STACK_SIZE); + if (p_stack) + { + + /* It is most efficient to disable interrupts for Nucleus for a short + time. Chances are we are doing this while interrupts are disabled + already during system initialization. + */ + old_level = NU_Control_Interrupts(NU_DISABLE_INTERRUPTS); + + /* It is a simplification here that once an HISR is set up for a particular + * vector it will never be set up again. This way if the init code is called + * more than once it is harmless (no memory leaks) + */ + while (p_hisr != NULL) + { + if (vector == p_hisr->vector) + { + NU_Control_Interrupts(old_level); + free(p_stack); + free(nucleus_hisr); + return; + } + p_hisr = p_hisr->next; + } + + /* Get a sys_hisr structure */ + p_hisr = (struct sys_hisr *) calloc(1,sizeof(struct sys_hisr)); + if (p_hisr) + { + p_hisr->next = hisrs; + p_hisr->vector = vector; + p_hisr->hisr = nucleus_hisr; + p_hisr->disablefun = dis_funct; + hisrs = p_hisr; + + NU_Control_Interrupts(old_level); + + num_hisr = (num_hisr + 1) % 100; + sprintf(hisr_name, "lwip%02d", num_hisr); + hisr_name[strlen(hisr_name)] = ' '; + + /* Ask Nucleus to create the HISR */ + status = NU_Create_HISR(p_hisr->hisr, + hisr_name, + isr_function, + 1, //Priority 0-2 + p_stack, + SYS_HISR_STACK_SIZE); + if (status == NU_SUCCESS) + { + /* Plug vector with system lisr now */ + NU_Register_LISR(vector, sys_arch_lisr, &old_lisr); + return; //Success + } + } + NU_Control_Interrupts(old_level); + } + } + /* Errors should be logged here */ + abort(); +} + +/*---------------------------------------------------------------------------------*/ +u32_t +sys_disable_interrupts(void) +{ + return NU_Control_Interrupts(NU_DISABLE_INTERRUPTS); +} + +/*---------------------------------------------------------------------------------*/ +void +sys_restore_interrupts(u32_t old_level) +{ + NU_Control_Interrupts(old_level); +} + +/********************************************************************* + * void sys_get_eth_addr(struct eth_addr *eth_addr) + * + * Get configured ethernet address from nvram and return it + * in a eth_addr structure. + *********************************************************************/ +void +sys_get_eth_addr(struct eth_addr *eth_addr) +{ + Cfg_lan *p_lan = config_get_lan_setup(); + + eth_addr->addr[0] = (u8_t) ((p_lan->etheraddrhi >> 16) & 0xff); + eth_addr->addr[1] = (u8_t) ((p_lan->etheraddrhi >> 8) & 0xff); + eth_addr->addr[2] = (u8_t) ((p_lan->etheraddrhi) & 0xff); + eth_addr->addr[3] = (u8_t) ((p_lan->etheraddrlo >> 16) & 0xff); + eth_addr->addr[4] = (u8_t) ((p_lan->etheraddrlo >> 8) & 0xff); + eth_addr->addr[5] = (u8_t) ((p_lan->etheraddrlo) & 0xff); +}