mirror of
https://github.com/dougg3/mac-rom-simm-programmer.git
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213 lines
13 KiB
C
213 lines
13 KiB
C
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/**************************************************************************//**
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* @file dac_reg.h
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* @version V1.00
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* @brief DAC register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __DAC_REG_H__
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#define __DAC_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup DAC Digital to Analog Converter (DAC)
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Memory Mapped Structure for DAC Controller
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@{
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*/
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typedef struct
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{
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/**
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* @var DAC_T::CTL
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* Offset: 0x00 DAC Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |DACEN |DAC Enable Bit
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* | | |0 = DAC is Disabled.
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* | | |1 = DAC is Enabled.
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* |[1] |DACIEN |DAC Interrupt Enable Bit
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* | | |0 = Interrupt is Disabled.
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* | | |1 = Interrupt is Enabled.
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* |[2] |DMAEN |DMA Mode Enable Bit
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* | | |0 = DMA mode Disabled.
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* | | |1 = DMA mode Enabled.
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* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
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* | | |0 = DMA underrun interrupt Disabled.
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* | | |1 = DMA underrun interrupt Enabled.
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* |[4] |TRGEN |Trigger Mode Enable Bit
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* | | |0 = DAC event trigger mode Disabled.
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* | | |1 = DAC event trigger mode Enabled.
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* |[7:5] |TRGSEL |Trigger Source Selection
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* | | |000 = Software trigger.
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* | | |001 = External pin DAC_ST trigger.
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* | | |010 = Timer 0 trigger.
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* | | |011 = Timer 1 trigger.
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* | | |100 = Timer 2 trigger.
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* | | |101 = Timer 3 trigger.
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* | | |Others = reserved.
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* |[8] |BYPASS |Bypass Buffer Mode
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* | | |0 = Output voltage buffer Enabled.
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* | | |1 = Output voltage buffer Disabled.
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* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
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* | | |0 = Right alignment.
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* | | |1 = Left alignment.
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* |[13:12] |ETRGSEL |External Pin Trigger Selection
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* | | |00 = Low level trigger.
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* | | |01 = High level trigger.
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* | | |10 = Falling edge trigger.
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* | | |11 = Rising edge trigger.
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* |[15:14] |BWSEL |DAC Data Bit-width Selection
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* | | |00 = data is 12 bits.
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* | | |01 = data is 8 bits.
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* | | |Others = reserved.
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* |[16] |GRPEN |DAC Group Mode Enable Bit
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* | | |0 = DAC0 and DAC1 are not grouped.
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* | | |1 = DAC0 and DAC1 are grouped.
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* | | |Note:This function only supports having two DAC channels.
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* @var DAC_T::SWTRG
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* Offset: 0x04 DAC Software Trigger Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |SWTRG |Software Trigger
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* | | |0 = Software trigger Disabled.
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* | | |1 = Software trigger Enabled.
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* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
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* @var DAC_T::DAT
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* Offset: 0x08 DAC Data Holding Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[15:0] |DACDAT |DAC 12-bit Holding Data
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* | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
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* | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
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* | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
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* | | |DAC 8-bit Holding Data
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* | | |The unused bits DAC_DAT[15:8] are ignored by DAC controller hardware.
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* | | |Note: Conversion data and DAC output data is 12-bit
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* @var DAC_T::DATOUT
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* Offset: 0x0C DAC Data Output Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |DATOUT |DAC 12-bit Output Data
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* | | |These bits are current digital data for DAC output conversion.
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* | | |It is loaded from DAC_DAT register and user cannot write it directly.
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* @var DAC_T::STATUS
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* Offset: 0x10 DAC Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |FINISH |DAC Conversion Complete Finish Flag
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* | | |0 = DAC is in conversion state.
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* | | |1 = DAC conversion finish.
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* | | |This bit set to 1 when conversion time counter counts to SETTLET
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* | | |It is cleared to 0 when DAC starts a new conversion
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* | | |User writes 1 to clear this bit to 0.
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* |[1] |DMAUDR |DMA Under Run Interrupt Flag
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* | | |0 = No DMA under-run error condition occurred.
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* | | |1 = DMA under-run error condition occurred.
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* | | |User writes 1 to clear this bit.
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* |[8] |BUSY |DAC Busy Flag (Read Only)
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* | | |0 = DAC is ready for next conversion.
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* | | |1 = DAC is busy in conversion.
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* | | |This is read only bit.
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* @var DAC_T::TCTL
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* Offset: 0x14 DAC Timing Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[9:0] |SETTLET |DAC Output Settling Time
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* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
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* | | |For example, DAC controller clock speed is 50MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x32.
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*/
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__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
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__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
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__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
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__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
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__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
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__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
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} DAC_T;
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/**
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@addtogroup DAC_CONST DAC Bit Field Definition
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Constant Definitions for DAC Controller
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@{ */
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#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
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#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
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#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
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#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
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#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
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#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
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#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
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#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
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#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
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#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
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#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
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#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
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#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
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#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
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#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
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#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
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#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
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#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
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#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
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#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
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#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
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#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
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#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
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#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
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#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
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#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
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#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
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#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
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#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
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#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
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#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
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#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
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#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
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#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
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#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
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#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
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/** @} DAC_CONST */
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/** @} end of DAC register group */
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/** @} end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __DAC_REG_H__ */
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