152 lines
9.1 KiB
C
152 lines
9.1 KiB
C
/**************************************************************************//**
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* @file crc_reg.h
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* @version V1.00
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* @brief CRC register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __CRC_REG_H__
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#define __CRC_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup CRC Cyclic Redundancy Check Controller (CRC)
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Memory Mapped Structure for CRC Controller
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@{
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*/
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typedef struct
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{
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/**
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* @var CRC_T::CTL
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* Offset: 0x00 CRC Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |CRCEN |CRC Channel Enable Bit
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* | | |0 = No effect.
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* | | |1 = CRC operation Enabled.
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* |[1] |CHKSINIT |Checksum Initialization
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* | | |0 = No effect.
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* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
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* | | |Note: This bit will be cleared automatically.
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* |[24] |DATREV |Write Data Bit Order Reverse
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* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
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* | | |0 = Bit order reversed for CRC write data in Disabled.
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* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
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* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
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* |[25] |CHKSREV |Checksum Bit Order Reverse
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* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
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* | | |0 = Bit order reverse for CRC checksum Disabled.
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* | | |1 = Bit order reverse for CRC checksum Enabled.
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* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
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* |[26] |DATFMT |Write Data 1's Complement
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* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
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* | | |0 = 1's complement for CRC writes data in Disabled.
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* | | |1 = 1's complement for CRC writes data in Enabled.
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* |[27] |CHKSFMT |Checksum 1's Complement
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* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
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* | | |0 = 1's complement for CRC checksum Disabled.
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* | | |1 = 1's complement for CRC checksum Enabled.
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* |[29:28] |DATLEN |CPU Write Data Length
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* | | |This field indicates the write data length.
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* | | |00 = Data length is 8-bit mode.
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* | | |01 = Data length is 16-bit mode.
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* | | |1x = Data length is 32-bit mode.
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* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
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* |[31:30] |CRCMODE |CRC Polynomial Mode
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* | | |This field indicates the CRC operation polynomial mode.
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* | | |00 = CRC-CCITT Polynomial mode.
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* | | |01 = CRC-8 Polynomial mode.
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* | | |10 = CRC-16 Polynomial mode.
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* | | |11 = CRC-32 Polynomial mode.
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* @var CRC_T::DAT
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* Offset: 0x04 CRC Write Data Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |DATA |CRC Write Data Bits
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* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
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* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
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* @var CRC_T::SEED
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* Offset: 0x08 CRC Seed Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |SEED |CRC Seed Value
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* | | |This field indicates the CRC seed value.
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* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
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* @var CRC_T::CHECKSUM
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* Offset: 0x0C CRC Checksum Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |CHECKSUM |CRC Checksum Results
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* | | |This field indicates the CRC checksum result.
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*/
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__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
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__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
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__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
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__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
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} CRC_T;
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/**
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@addtogroup CRC_CONST CRC Bit Field Definition
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Constant Definitions for CRC Controller
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@{ */
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#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
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#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
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#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
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#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
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#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
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#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
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#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
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#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
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#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
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#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
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#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
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#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
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#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
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#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
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#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
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#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
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#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
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#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
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#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
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#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
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#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
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#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
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/** @} CRC_CONST */
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/** @} end of CRC register group */
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/** @} end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __CRC_REG_H__ */
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