448 lines
31 KiB
C
448 lines
31 KiB
C
/**************************************************************************//**
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* @file fmc_reg.h
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* @version V1.00
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* @brief FMC register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __FMC_REG_H__
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#define __FMC_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup FMC Flash Memory Controller (FMC)
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Memory Mapped Structure for FMC Controller
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@{
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*/
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typedef struct
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{
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/**
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* @var FMC_T::ISPCTL
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* Offset: 0x00 ISP Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |ISPEN |ISP Enable Bit (Write Protect)
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* | | |ISP function enable bit. Set this bit to enable ISP function.
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* | | |0 = ISP function Disabled.
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* | | |1 = ISP function Enabled.
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* |[1] |BS |Boot Select (Write Protect)
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* | | |Set/clear this bit to select next booting from LDROM/APROM, respectively
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* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
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* | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
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* | | |0 = Booting from APROM.
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* | | |1 = Booting from LDROM.
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* |[3] |APUEN |APROM Update Enable Bit (Write Protect)
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* | | |0 = APROM cannot be updated when the chip runs in APROM.
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* | | |1 = APROM can be updated when the chip runs in APROM.
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
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* | | |0 = CONFIG cannot be updated.
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* | | |1 = CONFIG can be updated.
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
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* | | |LDROM update enable bit.
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* | | |0 = LDROM cannot be updated.
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* | | |1 = LDROM can be updated.
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* |[6] |ISPFF |ISP Fail Flag (Write Protect)
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* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
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* | | |This bit needs to be cleared by writing 1 to it.
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* | | |(1) APROM writes to itself if APUEN is set to 0.
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* | | |(2) LDROM writes to itself if LDUEN is set to 0.
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* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
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* | | |(4) Page Erase command at LOCK mode with ICE connection
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* | | |(5) Erase or Program command at brown-out detected
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* | | |(6) Destination address is illegal, such as over an available range.
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* | | |(7) Invalid ISP commands
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* | | |(8) ISP CMD in XOM region, except mass erase, page erase and chksum command
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* | | |(9) The wrong setting of page erase ISP CMD in XOM
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* | | |(10) Violate XOM setting one time protection
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* @var FMC_T::ISPADDR
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* Offset: 0x04 ISP Address Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |ISPADDR |ISP Address
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* | | |For Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
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* @var FMC_T::ISPDAT
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* Offset: 0x08 ISP Data Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |ISPDAT |ISP Data
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* | | |Write data to this register before ISP program operation.
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* | | |Read data from this register after ISP read operation.
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* | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment
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* | | |For ISP Read Checksum command, ISPDAT is the checksum result
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* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect.
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* @var FMC_T::ISPCMD
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* Offset: 0x0C ISP CMD Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[6:0] |CMD |ISP CMD
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* | | |ISP command table is shown below:
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* | | |0x00= FLASH Read.
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* | | |0x04= Read Unique ID.
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* | | |0x0B= Read Company ID.
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* | | |0x0C= Read Device ID.
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* | | |0x0D= Read Checksum.
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* | | |0x21= FLASH 32-bit Program.
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* | | |0x22= FLASH Page Erase.
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* | | |0x27= FLASH Multi-Word Program.
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* | | |0x28= Run Flash All-One Verification.
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* | | |0x2D= Run Checksum Calculation.
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* | | |0x2E= Vector Remap.
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* | | |The other commands are invalid.
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* @var FMC_T::ISPTRG
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* Offset: 0x10 ISP Trigger Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |ISPGO |ISP Start Trigger (Write Protect)
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* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
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* | | |0 = ISP operation is finished.
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* | | |1 = ISP is progressed.
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* @var FMC_T::FTCTL
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* Offset: 0x18 Flash Access Time Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[9] |CACHEINV |Flash Cache Invalidation (Write Protect)
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* | | |Write 1 to start cache invalidation. The value will be change to 0 once the process finishes.
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* | | |0 = Flash Cache Invalidation.(default)
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* | | |1 = Flash Cache Invalidation.
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* @var FMC_T::ISPSTS
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* Offset: 0x40 ISP Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |ISPBUSY |ISP Busy Flag (Read Only)
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* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
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* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
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* | | |0 = ISP operation is finished.
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* | | |1 = ISP is progressed.
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* |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
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* | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
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* | | |00 = LDROM with IAP mode.
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* | | |01 = LDROM without IAP mode.
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* | | |10 = APROM with IAP mode.
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* | | |11 = APROM without IAP mode.
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* |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
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* | | |This bit is set if data is mismatched at ISP programming verification
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* | | |This bit is clear by performing ISP Flash erase or ISP read CID operation
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* | | |0 = Flash Program is success.
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* | | |1 = Flash Program is fail. Program data is different with data in the Flash memory
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* |[6] |ISPFF |ISP Fail Flag (Write Protect)
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* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
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* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
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* | | |(1) APROM writes to itself if APUEN is set to 0.
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* | | |(2) LDROM writes to itself if LDUEN is set to 0.
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* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
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* | | |(4) Page Erase command at LOCK mode with ICE connection
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* | | |(5) Erase or Program command at brown-out detected
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* | | |(6) Destination address is illegal, such as over an available range.
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* | | |(7) Invalid ISP commands
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* | | |(8) ISP CMD in XOM region, except mass erase, page erase and chksum command
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* | | |(9) The wrong setting of page erase ISP CMD in XOM
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* | | |(10) Violate XOM setting one time protection
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* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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* |[7] |ALLONE |Flash All-one Verification Flag
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* | | |This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1
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* | | |0 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
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* | | |1 = All of Flash bits are 1 after "Run Flash All-One Verification" complete.
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* |[29:9] |VECMAP |Vector Page Mapping Address (Read Only)
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* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}.
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* | | |VECMAP [20:19] = 00 system vector address is mapped to Flash memory.
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* | | |VECMAP [20:19] = 10 system vector address is mapped to SRAM memory.
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* | | |VECMAP [18:12] should be 0.
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* @var FMC_T::CYCCTL
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* Offset: 0x4C Flash Access Cycle Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
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* | | |0001 = CPU access with zero wait cycle ; Flash access cycle is 1;.
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* | | |The HCLK working frequency range is <19MHz; Cache is disabled by hardware.
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* | | |0010 = CPU access with one wait cycles if cache miss; Flash access cycle is 2;.
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* | | | The optimized HCLK working frequency range is 18~33 MHz
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* | | |0011 = CPU access with two wait cycles if cahce miss; Flash access cycle is 3;.
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* | | | The optimized HCLK working frequency range is 33~50 MHz
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* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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* @var FMC_T::MPDAT0
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* Offset: 0x80 ISP Data0 Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |ISPDAT0 |ISP Data 0
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* | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
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* @var FMC_T::MPDAT1
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* Offset: 0x84 ISP Data1 Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |ISPDAT1 |ISP Data 1
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* | | |This register is the second 32-bit data for 64-bit/multi-word programming.
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* @var FMC_T::MPDAT2
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* Offset: 0x88 ISP Data2 Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |ISPDAT2 |ISP Data 2
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* | | |This register is the third 32-bit data for multi-word programming.
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* @var FMC_T::MPDAT3
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* Offset: 0x8C ISP Data3 Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |ISPDAT3 |ISP Data 3
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* | | |This register is the fourth 32-bit data for multi-word programming.
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* @var FMC_T::MPSTS
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* Offset: 0xC0 ISP Multi-program Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
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* | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
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* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
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* | | |0 = ISP Multi-Word program operation is finished.
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* | | |1 = ISP Multi-Word program operation is progressed.
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* |[1] |PPGO |ISP Multi-program Status (Read Only)
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* | | |0 = ISP multi-word program operation is not active.
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* | | |1 = ISP multi-word program operation is in progress.
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* |[2] |ISPFF |ISP Fail Flag (Read Only)
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* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
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* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
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* | | |(1) APROM writes to itself if APUEN is set to 0.
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* | | |(2) LDROM writes to itself if LDUEN is set to 0.
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* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
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* | | |(4) Page Erase command at LOCK mode with ICE connection
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* | | |(5) Erase or Program command at brown-out detected
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* | | |(6) Destination address is illegal, such as over an available range.
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* | | |(7) Invalid ISP commands
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* |[4] |D0 |ISP DATA 0 Flag (Read Only)
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* | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
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* | | |0 = FMC_MPDAT0 register is empty, or program to Flash complete.
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* | | |1 = FMC_MPDAT0 register has been written, and not program to Flash complete.
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* |[5] |D1 |ISP DATA 1 Flag (Read Only)
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* | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
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* | | |0 = FMC_MPDAT1 register is empty, or program to Flash complete.
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* | | |1 = FMC_MPDAT1 register has been written, and not program to Flash complete.
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* |[6] |D2 |ISP DATA 2 Flag (Read Only)
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* | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
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* | | |0 = FMC_MPDAT2 register is empty, or program to Flash complete.
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* | | |1 = FMC_MPDAT2 register has been written, and not program to Flash complete.
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* |[7] |D3 |ISP DATA 3 Flag (Read Only)
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* | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
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* | | |0 = FMC_MPDAT3 register is empty, or program to Flash complete.
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* | | |1 = FMC_MPDAT3 register has been written, and not program to Flash complete.
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* @var FMC_T::MPADDR
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* Offset: 0xC4 ISP Multi-program Address Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[31:0] |MPADDR |ISP Multi-word Program Address
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* | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
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* | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
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* @var FMC_T::XOMR0STS0
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* Offset: 0xD0 XOM Region 0 Status Register 0
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[23:0] |BASE |XOM Region 0 Base Address (Page-aligned)
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* | | |BASE is the base address of XOM Region 0.
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* @var FMC_T::XOMR0STS1
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* Offset: 0xD4 XOM Region 0 Status Register 1
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[8:0] |SIZE |XOM Region 0 Size (Page-aligned)
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* | | |SIZE is the page number of XOM Region 0.
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* @var FMC_T::XOMSTS
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* Offset: 0xE0 XOM Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |XOMR0ON |XOM Region 0 On
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* | | |XOM Region 0 active status.
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* | | |0 = No active.
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* | | |1 = XOM region 0 is active.
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* |[4] |XOMPEF |XOM Page Erase Function Fail
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* | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
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* | | |0 = Sucess.
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* | | |1 = Fail.
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*/
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__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
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__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
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__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
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__IO uint32_t ISPCMD; /*!< [0x000c] ISP CMD Register */
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__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
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__I uint32_t RESERVE0;
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__IO uint32_t FTCTL; /*!< [0x0018] Flash Access Time Control Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE1[9];
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/// @endcond //HIDDEN_SYMBOLS
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__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE2[2];
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/// @endcond //HIDDEN_SYMBOLS
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__IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE3[12];
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/// @endcond //HIDDEN_SYMBOLS
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__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
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__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
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__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
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__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE4[12];
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/// @endcond //HIDDEN_SYMBOLS
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__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-program Status Register */
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__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-program Address Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE5[2];
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/// @endcond //HIDDEN_SYMBOLS
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__I uint32_t XOMR0STS0; /*!< [0x00d0] XOM Region 0 Status Register 0 */
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__I uint32_t XOMR0STS1; /*!< [0x00d4] XOM Region 0 Status Register 1 */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE6[2];
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/// @endcond //HIDDEN_SYMBOLS
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__I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */
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} FMC_T;
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/**
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@addtogroup FMC_CONST FMC Bit Field Definition
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Constant Definitions for FMC Controller
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@{ */
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#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
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#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
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#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
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#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
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#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
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#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
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#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
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#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
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#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
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#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
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#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
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#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
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#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
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#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
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#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
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#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
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#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
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#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
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#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
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#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
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#define FMC_FTCTL_CACHEINV_Pos (9) /*!< FMC_T::FTCTL: CACHEINV Position */
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#define FMC_FTCTL_CACHEINV_Msk (0x1ul << FMC_FTCTL_CACHEINV_Pos) /*!< FMC_T::FTCTL: CACHEINV Mask */
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#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
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#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
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#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
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#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
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#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
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#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
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#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
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#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
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#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
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#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
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#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
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#define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
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#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
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#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
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#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
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#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
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#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
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#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
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#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
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#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
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#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
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#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
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#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
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#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
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#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
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#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
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#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
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#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
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#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
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#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
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#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
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#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
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#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
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#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
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#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
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#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
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#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
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#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
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#define FMC_XOMR0STS0_BASE_Pos (0) /*!< FMC_T::XOMR0STS0: BASE Position */
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#define FMC_XOMR0STS0_BASE_Msk (0xfffffful << FMC_XOMR0STS0_BASE_Pos) /*!< FMC_T::XOMR0STS0: BASE Mask */
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#define FMC_XOMR0STS1_SIZE_Pos (0) /*!< FMC_T::XOMR0STS1: SIZE Position */
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#define FMC_XOMR0STS1_SIZE_Msk (0x1fful << FMC_XOMR0STS1_SIZE_Pos) /*!< FMC_T::XOMR0STS1: SIZE Mask */
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#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */
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#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */
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#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */
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#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */
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/** @} FMC_CONST */
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/** @} end of FMC register group */
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/** @} end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __FMC_REG_H__ */
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