395 lines
13 KiB
ArmAsm
395 lines
13 KiB
ArmAsm
/****************************************************************************//**
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* @file startup_M251.S
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* @version V1.00
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* @brief CMSIS Cortex-M23 Core Device Startup File for M251
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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.syntax unified
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.arch armv8-m.base
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0x00000400
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x00000100
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vectors
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.align 2
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.globl __Vectors
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__Vectors:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.long BOD_IRQHandler /* 0: BOD */
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.long IRCTRIM_IRQHandler /* 1: IRC */
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.long PWRWU_IRQHandler /* 2: PWRWU */
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.long Default_Handler /* 3: Reserved */
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.long CLKFAIL_IRQHandler /* 4: CKFAIL */
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.long Default_Handler /* 5: Reserved */
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.long RTC_IRQHandler /* 6: RTC */
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.long TAMPER_IRQHandler /* 7: TAMPER */
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.long WDT_IRQHandler /* 8: WDT */
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.long WWDT_IRQHandler /* 9: WWDT */
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.long EINT0_IRQHandler /* 10: EINT0 */
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.long EINT1_IRQHandler /* 11: EINT1 */
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.long EINT2_IRQHandler /* 12: EINT2 */
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.long EINT3_IRQHandler /* 13: EINT3 */
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.long EINT4_IRQHandler /* 14: EINT4 */
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.long EINT5_IRQHandler /* 15: EINT5 */
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.long GPA_IRQHandler /* 16: GPA */
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.long GPB_IRQHandler /* 17: GPB */
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.long GPC_IRQHandler /* 18: GPC */
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.long GPD_IRQHandler /* 19: GPD */
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.long GPE_IRQHandler /* 20: GPE */
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.long GPF_IRQHandler /* 21: GPF */
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.long QSPI0_IRQHandler /* 22: QSPI0 */
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.long SPI0_IRQHandler /* 23: SPI0 */
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.long BRAKE0_IRQHandler /* 24: BRAKE0 */
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.long PWM0_P0_IRQHandler /* 25: EPWM0P0 */
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.long PWM0_P1_IRQHandler /* 26: EPWM0P1 */
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.long PWM0_P2_IRQHandler /* 27: EPWM0P2 */
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.long BRAKE1_IRQHandler /* 28: BRAKE1 */
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.long PWM1_P0_IRQHandler /* 29: EPWM1P0 */
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.long PWM1_P1_IRQHandler /* 30: EPWM1P1 */
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.long PWM1_P2_IRQHandler /* 31: EPWM1P2 */
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.long TMR0_IRQHandler /* 32: TIMER0 */
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.long TMR1_IRQHandler /* 33: TIMER1 */
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.long TMR2_IRQHandler /* 34: TIMER2 */
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.long TMR3_IRQHandler /* 35: TIMER3 */
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.long UART0_IRQHandler /* 36: UART0 */
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.long UART1_IRQHandler /* 37: UART1 */
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.long I2C0_IRQHandler /* 38: I2C0 */
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.long I2C1_IRQHandler /* 39: I2C1 */
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.long PDMA_IRQHandler /* 40: PDMA */
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.long DAC_IRQHandler /* 41: DAC */
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.long EADC_INT0_IRQHandler /* 42: EADC00 */
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.long EADC_INT1_IRQHandler /* 43: EADC01 */
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.long ACMP01_IRQHandler /* 44: ACMP */
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.long BPWM0_IRQHandler /* 45: BPWM0 */
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.long EADC_INT2_IRQHandler /* 46: EADC02 */
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.long EADC_INT3_IRQHandler /* 47: EADC03 */
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.long UART2_IRQHandler /* 48: UART2 */
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.long Default_Handler /* 49: Reserved */
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.long USCI0_IRQHandler /* 50: UCSI0 */
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.long SPI1_IRQHandler /* 51: SPI1 */
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.long USCI1_IRQHandler /* 52: USCI1 */
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.long USBD_IRQHandler /* 53: USBD */
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.long BPWM1_IRQHandler /* 54: BPWM1 */
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.long PSIO_IRQHandler /* 55: PSIO */
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.long Default_Handler /* 56: Reserved */
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.long CRPT_IRQHandler /* 57: CRPT */
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.long SC0_IRQHandler /* 58: SC0 */
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.long Default_Handler /* 59: Reserved */
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.long USCI2_IRQHandler /* 60: USCI2 */
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.long LCD_IRQHandler /* 61: LCD */
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.long OPA_IRQHandler /* 62: OPA */
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.long TK_IRQHandler /* 63: TK */
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.size __Vectors, . - __Vectors
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.text
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.thumb
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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* data to implement than the latter.
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* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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#ifdef __STARTUP_COPY_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of triplets, each of which specify:
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* offset 0: LMA of start of a section to copy from
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* offset 4: VMA of start of a section to copy to
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* offset 8: size of the section to copy. Must be multiply of 4
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r4, =__copy_table_start__
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ldr r5, =__copy_table_end__
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.L_loop0:
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cmp r4, r5
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bge .L_loop0_done
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ldr r1, [r4]
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ldr r2, [r4, #4]
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ldr r3, [r4, #8]
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.L_loop0_0:
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subs r3, #4
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blt .L_loop0_0_done
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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b .L_loop0_0
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.L_loop0_0_done:
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adds r4, #12
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b .L_loop0
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.L_loop0_done:
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#else
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .L_loop1_done
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.L_loop1:
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subs r3, #4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .L_loop1
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.L_loop1_done:
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#endif /*__STARTUP_COPY_MULTIPLE */
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#define __STARTUP_CLEAR_BSS
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* There are two schemes too. One can clear multiple BSS sections. Another
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* can only clear one section. The former is more size expensive than the
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* latter.
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*
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* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
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* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
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*/
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#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of tuples specifying:
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* offset 0: Start of a BSS section
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* offset 4: Size of this BSS section. Must be multiply of 4
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*/
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ldr r3, =__zero_table_start__
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ldr r4, =__zero_table_end__
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.L_loop2:
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cmp r3, r4
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bge .L_loop2_done
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ldr r1, [r3]
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ldr r2, [r3, #4]
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movs r0, 0
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.L_loop2_0:
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subs r2, #4
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str r0, [r1, r2]
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bgt .L_loop2_0
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adds r3, #8
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b .L_loop2
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.L_loop2_done:
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#elif defined (__STARTUP_CLEAR_BSS)
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/* Single BSS section scheme.
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*
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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subs r2, r1
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ble .L_loop3_done
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.L_loop3:
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subs r2, #4
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str r0, [r1, r2]
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bgt .L_loop3
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.L_loop3_done:
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#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
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/* Unlock Register */
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ldr r0, =0x40000100
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movw r1, 0x00000059
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str r1, [r0]
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movw r1, 0x00000016
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str r1, [r0]
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movw r1, 0x00000088
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str r1, [r0]
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#ifndef __NO_SYSTEM_INIT
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bl SystemInit
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#endif
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/* Init POR */
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#if 1
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ldr r0, =0x40000024
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movw r1, 0x00005AA5
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str r1, [r0]
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ldr r0, =0x400001EC
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str r1, [r0]
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#endif
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/* Lock register */
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ldr r0, =0x40000100
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movw r1, 0x00000000
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str r1, [r0]
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#define __START main
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#ifndef __START
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#define __START _start
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#endif
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bl __START
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler BOD_IRQHandler
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def_irq_handler IRCTRIM_IRQHandler
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def_irq_handler PWRWU_IRQHandler
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def_irq_handler CLKFAIL_IRQHandler
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def_irq_handler RTC_IRQHandler
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def_irq_handler TAMPER_IRQHandler
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def_irq_handler WDT_IRQHandler
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def_irq_handler WWDT_IRQHandler
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def_irq_handler EINT0_IRQHandler
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def_irq_handler EINT1_IRQHandler
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def_irq_handler EINT2_IRQHandler
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def_irq_handler EINT3_IRQHandler
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def_irq_handler EINT4_IRQHandler
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def_irq_handler EINT5_IRQHandler
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def_irq_handler GPA_IRQHandler
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def_irq_handler GPB_IRQHandler
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def_irq_handler GPC_IRQHandler
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def_irq_handler GPD_IRQHandler
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def_irq_handler GPE_IRQHandler
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def_irq_handler GPF_IRQHandler
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def_irq_handler QSPI0_IRQHandler
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def_irq_handler SPI0_IRQHandler
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def_irq_handler BRAKE0_IRQHandler
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def_irq_handler PWM0_P0_IRQHandler
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def_irq_handler PWM0_P1_IRQHandler
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def_irq_handler PWM0_P2_IRQHandler
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def_irq_handler BRAKE1_IRQHandler
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def_irq_handler PWM1_P0_IRQHandler
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def_irq_handler PWM1_P1_IRQHandler
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def_irq_handler PWM1_P2_IRQHandler
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def_irq_handler TMR0_IRQHandler
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def_irq_handler TMR1_IRQHandler
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def_irq_handler TMR2_IRQHandler
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def_irq_handler TMR3_IRQHandler
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def_irq_handler UART0_IRQHandler
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def_irq_handler UART1_IRQHandler
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def_irq_handler I2C0_IRQHandler
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def_irq_handler I2C1_IRQHandler
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def_irq_handler PDMA_IRQHandler
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def_irq_handler DAC_IRQHandler
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def_irq_handler EADC_INT0_IRQHandler
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def_irq_handler EADC_INT1_IRQHandler
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def_irq_handler ACMP01_IRQHandler
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def_irq_handler BPWM0_IRQHandler
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def_irq_handler EADC_INT2_IRQHandler
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def_irq_handler EADC_INT3_IRQHandler
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def_irq_handler UART2_IRQHandler
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def_irq_handler USCI0_IRQHandler
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def_irq_handler SPI1_IRQHandler
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def_irq_handler USCI1_IRQHandler
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def_irq_handler USBD_IRQHandler
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def_irq_handler BPWM1_IRQHandler
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def_irq_handler PSIO_IRQHandler
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def_irq_handler CRPT_IRQHandler
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def_irq_handler SC0_IRQHandler
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def_irq_handler USCI2_IRQHandler
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def_irq_handler LCD_IRQHandler
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def_irq_handler OPA_IRQHandler
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def_irq_handler TK_IRQHandler
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.end
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