mirror of
https://github.com/dougg3/mac-rom-simm-programmer.git
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293 lines
18 KiB
C
293 lines
18 KiB
C
/**************************************************************************//**
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* @file ebi_reg.h
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* @version V1.00
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* @brief EBI register definition header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __EBI_REG_H__
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#define __EBI_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup EBI External Bus Interface Controller (EBI)
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Memory Mapped Structure for EBI Controller
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@{
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*/
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typedef struct
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{
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/**
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* @var EBI_T::CTL0
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* Offset: 0x00 External Bus Interface Bank0 Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |EN |EBI Enable Bit
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* | | |This bit is the functional enable bit for EBI.
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* | | |0 = EBI function Disabled.
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* | | |1 = EBI function Enabled.
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* |[1] |DW16 |EBI Data Width 16-bit Select
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* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
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* | | |0 = EBI data width is 8-bit.
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* | | |1 = EBI data width is 16-bit.
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* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
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* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
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* | | |0 = Chip select pin (EBI_nCS) is active low.
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* | | |1 = Chip select pin (EBI_nCS) is active high.
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* |[4] |CACCESS |Continuous Data Access Mode
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* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
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* | | |0 = Continuous data access mode Disabled.
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* | | |1 = Continuous data access mode Enabled.
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* |[10:8] |MCLKDIV |External Output Clock Divider
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* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
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* | | |000 = HCLK/1.
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* | | |001 = HCLK/2.
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* | | |010 = HCLK/4.
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* | | |011 = HCLK/8.
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* | | |100 = HCLK/16.
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* | | |101 = HCLK/32.
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* | | |110 = HCLK/64.
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* | | |111 = HCLK/128.
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* |[18:16] |TALE |Extend Time of ALE
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* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
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* | | |tALE = (TALE+1)*EBI_MCLK.
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* | | |Note: This field only available in EBI_CTL0 register
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* |[24] |WBUFEN |EBI Write Buffer Enable Bit
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* | | |0 = EBI write buffer Disabled.
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* | | |1 = EBI write buffer Enabled.
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* | | |Note: This bit only available in EBI_CTL0 register
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* @var EBI_T::TCTL0
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* Offset: 0x04 External Bus Interface Bank0 Timing Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[7:3] |TACC |EBI Data Access Time
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* | | |TACC defines data access time (tACC).
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* | | |tACC = (TACC +1) * EBI_MCLK.
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* |[10:8] |TAHD |EBI Data Access Hold Time
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* | | |TAHD defines data access hold time (tAHD).
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* | | |tAHD = (TAHD +1) * EBI_MCLK.
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* |[15:12] |W2X |Idle Cycle After Write
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* | | |This field defines the number of W2X idle cycle.
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* | | |W2X idle cycle = (W2X * EBI_MCLK).
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* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
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* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
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* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
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* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
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* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
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* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
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* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
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* |[27:24] |R2R |Idle Cycle Between Read-to-read
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* | | |This field defines the number of R2R idle cycle.
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* | | |R2R idle cycle = (R2R * EBI_MCLK).
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* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
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* @var EBI_T::CTL1
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* Offset: 0x10 External Bus Interface Bank1 Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |EN |EBI Enable Bit
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* | | |This bit is the functional enable bit for EBI.
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* | | |0 = EBI function Disabled.
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* | | |1 = EBI function Enabled.
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* |[1] |DW16 |EBI Data Width 16-bit Select
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* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
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* | | |0 = EBI data width is 8-bit.
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* | | |1 = EBI data width is 16-bit.
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* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
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* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
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* | | |0 = Chip select pin (EBI_nCS) is active low.
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* | | |1 = Chip select pin (EBI_nCS) is active high.
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* |[4] |CACCESS |Continuous Data Access Mode
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* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
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* | | |0 = Continuous data access mode Disabled.
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* | | |1 = Continuous data access mode Enabled.
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* |[10:8] |MCLKDIV |External Output Clock Divider
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* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
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* | | |000 = HCLK/1.
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* | | |001 = HCLK/2.
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* | | |010 = HCLK/4.
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* | | |011 = HCLK/8.
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* | | |100 = HCLK/16.
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* | | |101 = HCLK/32.
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* | | |110 = HCLK/64.
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* | | |111 = HCLK/128.
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* |[18:16] |TALE |Extend Time of ALE
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* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
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* | | |tALE = (TALE+1)*EBI_MCLK.
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* | | |Note: This field only available in EBI_CTL0 register
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* |[24] |WBUFEN |EBI Write Buffer Enable Bit
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* | | |0 = EBI write buffer Disabled.
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* | | |1 = EBI write buffer Enabled.
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* | | |Note: This bit only available in EBI_CTL0 register
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* @var EBI_T::TCTL1
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* Offset: 0x14 External Bus Interface Bank1 Timing Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[7:3] |TACC |EBI Data Access Time
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* | | |TACC defines data access time (tACC).
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* | | |tACC = (TACC +1) * EBI_MCLK.
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* |[10:8] |TAHD |EBI Data Access Hold Time
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* | | |TAHD defines data access hold time (tAHD).
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* | | |tAHD = (TAHD +1) * EBI_MCLK.
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* |[15:12] |W2X |Idle Cycle After Write
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* | | |This field defines the number of W2X idle cycle.
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* | | |W2X idle cycle = (W2X * EBI_MCLK).
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* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
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* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
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* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
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* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
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* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
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* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
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* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
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* |[27:24] |R2R |Idle Cycle Between Read-to-read
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* | | |This field defines the number of R2R idle cycle.
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* | | |R2R idle cycle = (R2R * EBI_MCLK).
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* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
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* @var EBI_T::CTL2
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* Offset: 0x20 External Bus Interface Bank2 Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |EN |EBI Enable Bit
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* | | |This bit is the functional enable bit for EBI.
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* | | |0 = EBI function Disabled.
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* | | |1 = EBI function Enabled.
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* |[1] |DW16 |EBI Data Width 16-bit Select
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* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
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* | | |0 = EBI data width is 8-bit.
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* | | |1 = EBI data width is 16-bit.
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* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
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* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
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* | | |0 = Chip select pin (EBI_nCS) is active low.
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* | | |1 = Chip select pin (EBI_nCS) is active high.
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* |[4] |CACCESS |Continuous Data Access Mode
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* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
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* | | |0 = Continuous data access mode Disabled.
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* | | |1 = Continuous data access mode Enabled.
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* |[10:8] |MCLKDIV |External Output Clock Divider
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* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
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* | | |000 = HCLK/1.
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* | | |001 = HCLK/2.
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* | | |010 = HCLK/4.
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* | | |011 = HCLK/8.
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* | | |100 = HCLK/16.
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* | | |101 = HCLK/32.
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* | | |110 = HCLK/64.
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* | | |111 = HCLK/128.
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* |[18:16] |TALE |Extend Time of ALE
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* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
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* | | |tALE = (TALE+1)*EBI_MCLK.
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* | | |Note: This field only available in EBI_CTL0 register
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* |[24] |WBUFEN |EBI Write Buffer Enable Bit
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* | | |0 = EBI write buffer Disabled.
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* | | |1 = EBI write buffer Enabled.
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* | | |Note: This bit only available in EBI_CTL0 register
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* @var EBI_T::TCTL2
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* Offset: 0x24 External Bus Interface Bank2 Timing Control Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[7:3] |TACC |EBI Data Access Time
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* | | |TACC defines data access time (tACC).
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* | | |tACC = (TACC +1) * EBI_MCLK.
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* |[10:8] |TAHD |EBI Data Access Hold Time
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* | | |TAHD defines data access hold time (tAHD).
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* | | |tAHD = (TAHD +1) * EBI_MCLK.
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* |[15:12] |W2X |Idle Cycle After Write
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* | | |This field defines the number of W2X idle cycle.
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* | | |W2X idle cycle = (W2X * EBI_MCLK).
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* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
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* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
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* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
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* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
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* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
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* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
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* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
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* |[27:24] |R2R |Idle Cycle Between Read-to-read
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* | | |This field defines the number of R2R idle cycle.
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* | | |R2R idle cycle = (R2R * EBI_MCLK).
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* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
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*/
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__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
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__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE0[2];
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/// @endcond //HIDDEN_SYMBOLS
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__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
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__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
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/// @cond HIDDEN_SYMBOLS
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__I uint32_t RESERVE1[2];
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/// @endcond //HIDDEN_SYMBOLS
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__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
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__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
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} EBI_T;
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/**
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@addtogroup EBI_CONST EBI Bit Field Definition
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Constant Definitions for EBI Controller
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@{ */
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#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
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#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
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#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
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#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
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#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
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#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
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#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
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#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
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#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
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#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
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#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
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#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
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#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
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#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
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#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
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#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
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#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
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#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
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#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
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#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
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#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
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#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
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#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
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#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
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#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
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#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
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/** @} EBI_CONST */
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/** @} end of EBI register group */
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/** @} end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif /* __EBI_REG_H__ */
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