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https://github.com/dougg3/mac-rom-simm-programmer.git
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7d83075f10
This implements a USB CDC serial port using the Nuvoton USBD driver. The USB handling is based on Nuvoton's BSP sample code, especially the IRQ handlers and descriptor buffer configuration. The descriptors have been adapted to be similar to the AVR version, and RX/TX functions have been written to implement an API closer to LUFA, which is what the SIMM programmer common code needs.
469 lines
12 KiB
C
469 lines
12 KiB
C
/*
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* usbcdc.c
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*
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* Created on: Jun 19, 2023
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* Author: Doug
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*
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* Copyright (C) 2011-2023 Doug Brown
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*
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* Portions of this code also came from Nuvoton's BSP, originally
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* licensed as Apache-2.0:
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*
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*/
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#include "usbcdc_hw.h"
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#include <stdbool.h>
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// Undocumented register for HIRC trim from Nuvoton's samples
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#define TRIM_INIT (SYS_BASE + 0x118)
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#define SET_LINE_CODE 0x20
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#define GET_LINE_CODE 0x21
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#define SET_CONTROL_LINE_STATE 0x22
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/// Setup buffer uses first 8 bytes of USB SRAM
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#define SETUP_BUF_BASE 0
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#define SETUP_BUF_LEN 8
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/// EP0 and EP1 share the same USB SRAM, 64 bytes of control
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#define EP0_BUF_BASE (SETUP_BUF_BASE + SETUP_BUF_LEN)
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#define EP0_BUF_LEN EP0_MAX_PKT_SIZE
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#define EP1_BUF_BASE (SETUP_BUF_BASE + SETUP_BUF_LEN)
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#define EP1_BUF_LEN EP1_MAX_PKT_SIZE
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/// EP2 uses 8 bytes for interrupt IN (not really used though)
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#define EP2_BUF_BASE (EP1_BUF_BASE + EP1_BUF_LEN)
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#define EP2_BUF_LEN EP2_MAX_PKT_SIZE
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/// EP3 uses 64 bytes for bulk IN
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#define EP3_BUF_BASE (EP2_BUF_BASE + EP2_BUF_LEN)
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#define EP3_BUF_LEN EP3_MAX_PKT_SIZE
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/// EP4 uses 64 bytes for bulk OUT
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#define EP4_BUF_BASE (EP3_BUF_BASE + EP3_BUF_LEN)
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#define EP4_BUF_LEN EP4_MAX_PKT_SIZE
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/// Struct to represent the current line coding
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typedef struct
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{
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uint32_t baudRate; // Baud rate
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uint8_t stopBits; // stop bit
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uint8_t parity; // parity
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uint8_t dataBits; // data bits
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} CDCLineCoding;
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static void USBCDC_SendDataInBuffer(void);
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static void USBCDC_InitEndpoints(void);
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static void USBCDC_ClassRequest(void);
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/// Default HIRC trim value in case of errors
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static uint32_t trimInit;
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/// Toggle flag for ensuring the received endpoint 4 packet is the expected one
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static volatile uint32_t ep4OutToggle = 0;
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/// Line coding for CDC device, not used by this firmware
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static CDCLineCoding cdcLineCoding = {0, 0, 0, 0};
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/// Control signal for CDC device, not used by this firmware
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static uint16_t cdcCtrlSignal;
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/// Buffer to send to the CDC serial port
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static uint8_t cdcTxBuf[EP3_MAX_PKT_SIZE];
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/// Current position in the TX buffer
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static uint32_t cdcTxBufPos = 0;
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/// Flag that is true if a TX is currently active
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static volatile bool cdcTxActive = false;
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/// Buffer we read into
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static uint8_t cdcRxBuf[EP4_MAX_PKT_SIZE];
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/// Current length of RX buffer
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static uint32_t cdcRxLen = 0;
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/// Current position into RX buffer
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static uint32_t cdcRxPos = 0;
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/// Flag that is true if new RX data is ready to read
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static volatile bool cdcRxReady = false;
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/** Initializes the USB CDC serial port
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*
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*/
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void USBCDC_Init(void)
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{
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// Set up USB
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USBD_Open(&gsInfo, USBCDC_ClassRequest);
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USBCDC_InitEndpoints();
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USBD_Start();
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NVIC_EnableIRQ(USBD_IRQn);
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// Backup the default trim value, go back to it if there's an error
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trimInit = M32(TRIM_INIT);
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// Clear USB SOF flag; it will be used to detect if we have a USB
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// signal available to use for HIRC trim
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USBD_CLR_INT_FLAG(USBD_INTSTS_SOFIF_Msk);
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}
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/** Performs any necessary periodic tasks for the USB CDC serial port
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*
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*/
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void USBCDC_Check(void)
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{
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// If we haven't enabled auto trim, and we have a USB signal available,
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// then do it!
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if (((SYS->HIRCTRIMCTL & SYS_HIRCTRIMCTL_FREQSEL_Msk) != 0x1) &&
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(USBD->INTSTS & USBD_INTSTS_SOFIF_Msk))
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{
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// Clear SOF flag for next time
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USBD_CLR_INT_FLAG(USBD_INTSTS_SOFIF_Msk);
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// Start USB trim:
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// - HIRC trim reference is USB clock
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// - Enable auto trim, and trim to 48 MHz
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// - Use 4 cycles for trimming
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// - Boundary enabled (value = 10)
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SYS->HIRCTRIMCTL = (0x1UL << SYS_HIRCTRIMCTL_REFCKSEL_Pos)
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| (0x1UL << SYS_HIRCTRIMCTL_FREQSEL_Pos)
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| (0x0UL << SYS_HIRCTRIMCTL_LOOPSEL_Pos)
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| (0x1UL << SYS_HIRCTRIMCTL_BOUNDEN_Pos)
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| (10UL << SYS_HIRCTRIMCTL_BOUNDARY_Pos);
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}
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// If we detect a clock error or trim failure, disable auto trim. We can try again later.
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if (SYS->HIRCTRIMSTS & (SYS_HIRCTRIMSTS_CLKERIF_Msk | SYS_HIRCTRIMSTS_TFAILIF_Msk))
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{
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// Restore original trim value we read at startup
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M32(TRIM_INIT) = trimInit;
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// Disable USB trim
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SYS->HIRCTRIMCTL = 0;
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// Clear the error flags
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SYS->HIRCTRIMSTS = SYS_HIRCTRIMSTS_CLKERIF_Msk | SYS_HIRCTRIMSTS_TFAILIF_Msk;
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// Clear the SOF flag so the next time it's set we know we have a USB signal
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USBD_CLR_INT_FLAG(USBD_INTSTS_SOFIF_Msk);
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}
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// Flush the USB CDC port every main loop just like LUFA does
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USBCDC_Flush();
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}
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/** Sends a byte out the USB serial port
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*
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* @param b The byte
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*/
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void USBCDC_SendByte(uint8_t b)
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{
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// Fill up our buffer to send out the USB serial port
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cdcTxBuf[cdcTxBufPos++] = b;
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if (cdcTxBufPos == EP3_MAX_PKT_SIZE)
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{
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// If we reached a full packet size, send the data in the buffer
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USBCDC_SendDataInBuffer();
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}
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}
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/** Reads a byte from the USB serial port, if available
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*
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* @return The byte, or -1 if there is nothing available
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*/
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int16_t USBCDC_ReadByte(void)
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{
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// Assume not ready
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int16_t ret = -1;
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// If we have data ready to read out of the USB controller's endpoint buffer, grab it now
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if (cdcRxLen == 0 && cdcRxReady)
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{
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// Flag that we handled the read event
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cdcRxReady = false;
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// Reset our read pointer just in case
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cdcRxPos = 0;
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// Read all of the data out from the USB controller
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cdcRxLen = USBD_GET_PAYLOAD_LEN(EP4);
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USBD_MemCopy(cdcRxBuf, (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP4)), cdcRxLen);
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// We grabbed all of the packet data, so tell the USB controller we're done with it
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USBD_SET_PAYLOAD_LEN(EP4, EP4_MAX_PKT_SIZE);
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}
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// If we have something left in our buffer since the last read, use it
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if (cdcRxLen > 0)
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{
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ret = cdcRxBuf[cdcRxPos++];
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// If we finished reading from the buffer, mark it as finished.
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if (cdcRxPos == cdcRxLen)
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{
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cdcRxPos = 0;
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cdcRxLen = 0;
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}
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}
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return ret;
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}
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/** Sends out any remaining data in the TX buffer
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*
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*/
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void USBCDC_Flush(void)
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{
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// If we have something waiting to send, send it out now
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if (cdcTxBufPos > 0)
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{
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bool needsZLP = cdcTxBufPos == EP3_MAX_PKT_SIZE;
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USBCDC_SendDataInBuffer();
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// If we are flushing after sending a full packet of data,
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// send a ZLP afterward to indicate end of transmit to host
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if (needsZLP)
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{
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USBCDC_SendDataInBuffer();
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}
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}
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}
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/** Sends the data in the EP3 TX buffer to the host
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*
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*/
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static void USBCDC_SendDataInBuffer(void)
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{
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// Wait for any previous transmit to finish first
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while (cdcTxActive);
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// Send out the packet
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USBD_MemCopy((uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP3)), cdcTxBuf, cdcTxBufPos);
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cdcTxActive = true;
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USBD_SET_PAYLOAD_LEN(EP3, cdcTxBufPos);
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// Reset our buffer position; we've given all the data to the USB controller
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cdcTxBufPos = 0;
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}
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/** IRQ handler called when USB endpoint 3 is ready (CDC TX data finished transferring)
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*
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*/
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void EP3_Handler(void)
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{
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// All we have to do is flag that we no longer have an active transmission.
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// USBCDC_SendDataInBuffer() will handle the rest.
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cdcTxActive = false;
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}
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/** IRQ handler called when USB endpoint 4 is ready (CDC RX data ready to read)
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*
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*/
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void EP4_Handler(void)
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{
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// Verify the toggle has changed. If it's still the same, re-request the data.
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if (ep4OutToggle == (USBD->EPSTS0 & USBD_EPSTS0_EPSTS4_Msk))
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{
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USBD_SET_PAYLOAD_LEN(EP4, EP4_MAX_PKT_SIZE);
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}
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// Toggle changed, so we're good to go. Toggle for next time and flag that we
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// have data ready to read. USBCDC_ReadByte() will handle the rest.
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else
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{
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ep4OutToggle = USBD->EPSTS0 & USBD_EPSTS0_EPSTS4_Msk;
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cdcRxReady = true;
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}
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}
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/** Main IRQ handler for USB device controller
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*
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*/
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void USBD_IRQHandler(void)
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{
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uint32_t intStatus = USBD_GET_INT_FLAG();
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uint32_t busState = USBD_GET_BUS_STATE();
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// Bus interrupt
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if (intStatus & USBD_INTSTS_BUSIF_Msk)
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{
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// Clear the flag
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USBD_CLR_INT_FLAG(USBD_INTSTS_BUSIF_Msk);
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// The bus was reset - SE0 status for long enough
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if (busState & USBD_STATE_USBRST)
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{
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// Enable USB, reset everything
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USBD_ENABLE_USB();
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USBD_SwReset();
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ep4OutToggle = 0;
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}
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// Entered suspend status (bus idle)
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if (busState & USBD_STATE_SUSPEND)
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{
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// Disable PHY while we're suspended
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USBD_DISABLE_PHY();
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}
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if (busState & USBD_STATE_RESUME)
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{
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// Re-enable USB (mainly just the PHY is what we want)
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USBD_ENABLE_USB();
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}
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}
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// USB event
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if (intStatus & USBD_INTSTS_USBIF_Msk)
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{
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// Setup packet?
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if (intStatus & USBD_INTSTS_SETUP_Msk)
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{
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// Clear the flag...
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USBD_CLR_INT_FLAG(USBD_INTSTS_SETUP);
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// Stop EP0 and EP1 which are the control endpoints
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USBD_STOP_TRANSACTION(EP0);
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USBD_STOP_TRANSACTION(EP1);
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// Now handle the received setup packet
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USBD_ProcessSetupPacket();
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}
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// EP0 - control in
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if (intStatus & USBD_INTSTS_EPEVT0_Msk)
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{
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USBD_CLR_INT_FLAG(USBD_INTSTS_EPEVT0_Msk);
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USBD_CtrlIn();
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}
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// EP1 - control out
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if (intStatus & USBD_INTSTS_EPEVT1_Msk)
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{
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USBD_CLR_INT_FLAG(USBD_INTSTS_EPEVT1_Msk);
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USBD_CtrlOut();
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}
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// Do nothing for EP2 for now
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// EP3 - bulk in for CDC data
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if (intStatus & USBD_INTSTS_EPEVT3_Msk)
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{
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USBD_CLR_INT_FLAG(USBD_INTSTS_EPEVT3_Msk);
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EP3_Handler();
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}
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// EP4 - bulk out for CDC data
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if (intStatus & USBD_INTSTS_EPEVT4_Msk)
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{
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USBD_CLR_INT_FLAG(USBD_INTSTS_EPEVT4_Msk);
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EP4_Handler();
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}
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}
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}
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/** Initializes endpoint buffers in USB SRAM
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*
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*/
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void USBCDC_InitEndpoints(void)
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{
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// First 8 bytes are for setup packets
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USBD->STBUFSEG = SETUP_BUF_BASE;
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// EP0 = control IN, address 0, 64 bytes
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USBD_CONFIG_EP(EP0, USBD_CFG_CSTALL | USBD_CFG_EPMODE_IN | 0);
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USBD_SET_EP_BUF_ADDR(EP0, EP0_BUF_BASE);
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// EP1 = control OUT, address 0, uses same 64 bytes as control IN
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USBD_CONFIG_EP(EP1, USBD_CFG_CSTALL | USBD_CFG_EPMODE_OUT | 0);
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USBD_SET_EP_BUF_ADDR(EP1, EP1_BUF_BASE);
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// EP2 = interrupt IN, address 2, 8 bytes
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USBD_CONFIG_EP(EP2, USBD_CFG_EPMODE_IN | INT_IN_EP_NUM);
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USBD_SET_EP_BUF_ADDR(EP2, EP2_BUF_BASE);
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// EP3 = bulk IN, address 3, 64 bytes
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USBD_CONFIG_EP(EP3, USBD_CFG_EPMODE_IN | BULK_IN_EP_NUM);
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USBD_SET_EP_BUF_ADDR(EP3, EP3_BUF_BASE);
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// EP4 = bulk OUT, address 4, 64 bytes
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USBD_CONFIG_EP(EP4, USBD_CFG_EPMODE_OUT | BULK_OUT_EP_NUM);
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USBD_SET_EP_BUF_ADDR(EP4, EP4_BUF_BASE);
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// Mark that we are able to receive on EP4
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USBD_SET_PAYLOAD_LEN(EP4, EP4_MAX_PKT_SIZE);
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}
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/** USB class request callback for CDC device
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*
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*/
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void USBCDC_ClassRequest(void)
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{
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uint8_t buf[8];
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// Grab the setup packet...
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USBD_GetSetupPacket(buf);
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// Device to host?
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if (buf[0] & 0x80)
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{
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switch (buf[1])
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{
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case GET_LINE_CODE:
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if (buf[4] == 0)
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{
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USBD_MemCopy((uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)), (uint8_t *)&cdcLineCoding, 7);
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}
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// Data stage
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USBD_SET_DATA1(EP0);
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USBD_SET_PAYLOAD_LEN(EP0, 7);
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// Status stage
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USBD_PrepareCtrlOut(0, 0);
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break;
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default:
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// Stall
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USBD_SET_EP_STALL(EP0);
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USBD_SET_EP_STALL(EP1);
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break;
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}
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}
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// Host to device
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else
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{
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switch (buf[1])
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{
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case SET_CONTROL_LINE_STATE:
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if (buf[4] == 0)
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{
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cdcCtrlSignal = (buf[3] << 8) | buf[2];
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}
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// Status stage
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USBD_SET_DATA1(EP0);
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USBD_SET_PAYLOAD_LEN(EP0, 0);
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break;
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case SET_LINE_CODE:
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if (buf[4] == 0)
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{
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USBD_PrepareCtrlOut((uint8_t *)&cdcLineCoding, 7);
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}
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// Status stage
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USBD_SET_DATA1(EP0);
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USBD_SET_PAYLOAD_LEN(EP0, 0);
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break;
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default:
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// Stall
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USBD_SET_EP_STALL(EP0);
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USBD_SET_EP_STALL(EP1);
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break;
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}
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}
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}
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